i.MX6 IPU di0_erm_vsync_sel

[sugiyamatoshihi]

Hi, 

I have a question di0_erm_vsync_sel bit in IPUx_DI0_GENERAL register.

it described that ' The error recovery block detect a case where the DI's VSYNC is asserted before the EOF.'

I suppose EOF is generated in DI.

Where the EOF comes? 

Best Regards,

Sugiyama

[art]

The di0_erm_vsync_sel bit is meant to indicate a de-synchronization between DI and IDMAC (so, here the EOF control comes from IDMAC).

Have a great day,
Artur

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[sugiyamatoshihi]

HI, Artur,

Thank you for the answer.

I wonder how the source choose? What is the difference before and after DI's VSYNC?

Best Regards,

Sugiyama