i.MX6 IPU IPUx_DI0_DW_SET2

[sugiyamatoshihi]

Hi, 

I have a question about IPUx_DI0_DW_SET2_i.

What timing is refer to di0_data_cnt_down2_i, and di0_data_cnt_up2_i timing.

If it use IPUx_DI0_DW_GEN_2, which counter is refer to IPUx_DI0_DW_SET2?

Best Regards,

Sugiyama

[art]

Please refer to the Section 37.4.10.3 "Timing generator", especially, to the Figure 37-41 "DI waveform's main parameters", of the i.MX6Dual/Quad Reference Manual document. It explains in details the waveform generation parameters.

Best Regards,

Artur

[sugiyamatoshihi]

Hi Artur,

I read it but, I cannot explain DRDY behavior. Regarding to Figure 37-41, I considered the behavior of DRDY, bu I cannot understood.

I attached the behavior of DRDY, It cannot change the DRDY timing. what does this register control?

Best Regards

Suiyama

[art]

As the Section 37.4.10.3 "Timing generator" says, the DOWN counter value must be always greater than UP counter value for normal timing control. Please always follow this condition.

Best Regards,
Artur

[sugiyamatoshihi]

Hi, Artur,

I understand that.

I'd like to reset the questions.

My original question is how to set di0_data_cnt_up3_0 and di0_data_down3_0? Then,

1. What signal does these counter di0_data_cnt_up3_0 and di0_data_down3_0 use?  You answered HSP_CLK once, but according to Figure 37-41, it seems PIN_A base timer is DI_CLK.

2. In that case, does di0_data_cnt_up3_0 and di0_data_down3_0 registers use fractional part? If so, how many bits is fractional part.

After you mentioned it is refer to Figure 37-41,

There are questions.

1. What signal is PIN_15 time base (PIN_A timebase in Fig.)  Is it HSP_CLK or DI_CLK?

2. What is the count clock of up/down (di0_data_cnt_up3_0 and di0_data_down3_0) for PIN_15 (PIN_A in Fig.) ? It must be faster than PIN_A timebase.

Best Regards,

Sugiyama

[art]

As the Section 37.4.10.3 "Timing generator" says, the DI clock is derived from either the HSP_CLK clock (typically) or external clock. Then, the fundamental DI timebase is derived from the DI clock by the DI#_DISP_CLK_PERIOD and DI#_DISP_CLK_OFFSET parameters. The timebase for PIN_x waveform can be either fundamental timebase or another PIN_y waveform.

As for the PIN_11 to PIN_17 function (these are some special purpose asynchronous waveform pins), please refer to the Section 37.4.10.4 "Waveform settings for asynchronous interface pins".

The DI#_DATA_CNT_UPx_y and DI#_DATA_CNT_DOWNx_y counters have no fractional part.

Best Regards,

Artur

[sugiyamatoshihi]

Hi,  Artur,

Thank you for the answer.

Do you means DI#_DATA_CNT_UPx_y  and DI#_DATA_CNT_DOWNx_y  count by DI_CLK or anther PIN_y?

How does that clock define? 

Best Regards,

Sugiyama

[art]

The only clock option for the DI#_DATA_CNT_UPx_y and DI#_DATA_CNT_DOWNx_y counters is DI_CLK.

[sugiyamatoshihi]

Hi, Artur,

It is simple question.

If  DI#_DATA_CNT_UPx_y=0 and DI#_DATA_CNT_DOWNx_y=2,  does it divide DISP CLK

 into 2? 

Then that clock synchronize with PIN15 signal?

Best Regards,

Sugiyama

[sugiyamatoshihi]

Hi Artur,

Thank you for the answer.

I understood.

However I have one question.

I attache the waveform. Which is correct A or B that is the case of  IPUx_DI_DW_SETx_y attached.

Best Regards,

Sugiyama

[sugiyamatoshihi]

Hi, Artur,

Could you answer the question?

Best Regards,

Sugiyama

[sugiyamatoshihi]

Hi, Artur,

Regarding to Figure 37-41, 

What is the PIN_A timebase for PIN15  DRDY signal?

What signal does it input to counter? You previously mentioned HSP_CLK, so I suppose cnt_up/cnt_down point is counted by HSP_CLK, but counter value didn't affect DRDY signal timing refer to Hsync.   

Best Regards,

Sugiyama

[art]

The edges of the waveforms, generated according to the IPUx_DI0_DW_SETx_i register settings, are referred to the main IPU clock HSP_CLK.

Have a great day,
Artur

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[sugiyamatoshihi]

Hi, Artur,

Thank you for the answer.

One more question, the counter value of di0_data_cnt_down3_i and di0_data_cnt_up3_i are 9 bits each. 

That counter up/down values are using fractional part? If so, how many bit use for fractional?

Best Regards,

Sugiyama 

[art]

The di0_data_cnt_downx_i and di0_data_cnt_upx_i fields are not the up/down counters. These are the constant (pre-programmed) fields that define the positions of the falling (di0_data_cnt_downx_i) and rising (di0_data_cnt_upx_i) edge of the corresponding waveform in a number of main IPU clocks relatively to the waveform's triggering point.

Best Regards,

Artur

[sugiyamatoshihi]

Hi, Artur,

I understood it is not counter, it is specify the rising edge timing and falling edge timing.

I'm little confusing. 

DRDY signal is output from PIN15 by set di0_pt_4_i. and DRDY wave is generated by DI0_DW_SE3_i..

Then, I tried to change the value of di0_data_cnt_down3_i, however only when di0_data_cnt_up3_i is lager than 2, DRDY is output and rising/falling edge of DRDY didn't change by the value of di0_data_cnt_down3_i and  di0_data_cnt_up3_i.

1. What timing is refer to up/down timing? Refer to base timer or counter #1 or .....? How it is specify? 

2. What timing does these register control? I couldn't see any timing change.

3. Is it really HSP clock is reference clock? It may change according to dix_clk_ext bit that use DI clock?

4. Is there fractional part, like  di1_cnt_up_1 in IPUx_DI1_SW_GEN1_1? 

Best Regards,

Sugiyama

[art]

What exactly values of di0_data_cnt_down3_i and di0_data_cnt_up3_i do you use? What is the initial DRDY signal state Low or High? Please specify.

Best Regards,

Artur

[b50231katsuhiro]

Hi art‌

Could you please follow-up his question?

[sugiyamatoshihi]

Hi,

I checked the waveform of DRDY of Parallel Display CLAA-WVGA with SABRESDB. It is out put DRDY to PIN14.

I observed a waveform of IPU1_DI0_SET3 output to pt_

Then I checked the register value of IPU1_DI0_SET3 value. That is 0x00020000. WhenI changed value to 000f0000.

Nothing happens but if I set 0x0, DRDY wave doesn't output, signal stays high. However, when di0_data_cnt_up3_i is lager than 2, no DRDY output. Also it must be di0_data_cnt_down3_i is lager than di0_data_cnt_up3_i.

Can someone know what clock is refer to this position?

Best Regards,

Sugiyama