Hi everyone,
How could I know about i.MX6 output timing between CK and ADDR/CMD?
For DQ or DQS, I found out about Read calibration or Write calibration, but I couldn't see about CK and ADDR/CMD.
I need these parameters for SI Simulation.
Thanks in advance for any help!
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Hi Rita_Wang,
Thank you for Replying.
We have adapted the script to our design and have done stress checks.
However, as the number of prototypes increased, some prototypes did not boot Linux or hung during operation. In addition, the i.MX6 and DDR of those defective products were prone to defects when warmed up.
We are considering the possibility that the defects may be caused by PVT variations and would like to perform SI simulations to check for SI problems.
We have the IBIS model and board S-parameters already obtained, the rest we need is the timing parameters.
So please let me know the Output Timing Parameter of CK-ADDR/CMD.
If using LPDDR2, CA-Bus delay is showd in register WRCADL.
For DDR3 there is no register since no training for it in JEDEC.
The delay from CK to CA is controlled by routing rules. You could find it in HDG.