i.MX6 - GPIO Bit Lane Issue

[PaulDeMetrotion]

I have four GPIO bits that I have defined as inputs and all have external pull-ups so I would expect to read a one on all bits.

Here is my device tree configuration:

                MX6QDL_PAD_GPIO_3__GPIO1_IO03          0x80000000      // gpio0

                MX6QDL_PAD_GPIO_4__GPIO1_IO04          0x80000000      // gpio1

                MX6QDL_PAD_GPIO_5__GPIO1_IO05          0x80000000      // gpio2

                MX6QDL_PAD_GPIO_6__GPIO1_IO06          0x80000000      // gpio3

When I actaully read the values, the bits are set but they are still in their register bit alignment as shown.

root@imx6soloc421:/sys/class/gpio# echo in > gpio3/direction

root@imx6soloc421:/sys/class/gpio# echo in > gpio4/direction

root@imx6soloc421:/sys/class/gpio# echo in > gpio5/direction

root@imx6soloc421:/sys/class/gpio# echo in > gpio6/direction

root@imx6soloc421:/sys/class/gpio# cat gpio3/value

8

root@imx6soloc421:/sys/class/gpio# cat gpio4/value

16

root@imx6soloc421:/sys/class/gpio# cat gpio5/value

32

root@imx6soloc421:/sys/class/gpio# cat gpio6/value

64

Anybody know why this is happening?

[Carlos_Musich]

Hi Paul,

It seems to me that you are mixing 2 different BSPs. I find strange that on one side you have in your device tree configuration 'MX6QDL'. However on the other side you have root@imxsoloc, so I wonder what BSP are you using? Is it a BSP provided by NXP?

Regards,

Carlos

[PaulDeMetrotion]

The device uses an i.MX6 Solo device which uses the i.MX6 DL iomux settings.

[Carlos_Musich]

Is it your own BSP?