i.MX6 EIM WE44 timing.

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i.MX6 EIM WE44 timing.

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Senior Contributor I

Hi community,

We have a question about i.MX6DQ EIM.

Please see Figure 18 in IMX6DQCEC Rev.4.

The WE44 is defined as "EIM_CSx_B Invalid to Input Data Invalid".

On the other hand, I confirmed that data is "latched Data are latched at the recent rising edge (of internal clock) before OE or CS going HIGH (inactive) ; whoever comes first" in i.MX6DQ EIM data latch timing in async read access. .

So I think it is OK if EIM_DATA is kept when OE going inactive in the case of OE going inactive before CS going inactive, even if EIM_DATA is not kept on the timing CS going invalid.

(in other words, is it OK the following image timing)

EIM_timing.png

Is this right?

Best Regards,

Satoshi Shimoda

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NXP TechSupport
NXP TechSupport

Hi Satoshi

you are right, in such case it is OK for EIM_DATA is kept when OE going inactive,

though EIM_DATA is not kept on the timing CS going invalid.

Best regards

igor

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NXP TechSupport
NXP TechSupport

Hi Satoshi

you are right, in such case it is OK for EIM_DATA is kept when OE going inactive,

though EIM_DATA is not kept on the timing CS going invalid.

Best regards

igor

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Note: If this post answers your question, please click the Correct Answer button. Thank you!

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