i.MX6 Dual interfacing with 8 bit Parallel Camera MT9Dxxx series

[jhalife]

Hi, we are working on a medical design project. We are planning to use iMX6 Dual processor interfaced with Aptina Imaging sensor MT9Dxxx series on Camera Parallel Port Interface. Our selected sensor operates similar to MT9P031 camera

i.e. It  uses a Line Valid (LV) signal and Frame Valid (FV) signal instead of a single HSYNC and VSYNC pulse indicating the start of a line/frame. The FV signal remains active through the entire frame transfer

and so it does not match the timing diagrams shown in the Document #:IMX6DQAEC Rev.4, 07/2015

"4.11.10.2.2 Gated Clock Mode" which indicate HSYNC/VSYNC as having a single pulse in start of frame/line

We wanted to know if i.MX6D IPU engine can be used to process data from this image sensor directly? can this problem be taken care in software or will this need additional hardware?

Our understanding is since IPU engine is edge triggered so i.MX6 engine might support interfacing camera directly to CSI Parallel port interface.

Kindly guide us on this. Thanks.

[yyuan]

HI

   I have the same problem,Can you help me to explain this sequence diagram?

   There are some confusing points in the manual.

   Vsysc is the edge trigger?What is hysnc?Is it also edge triggered from the timing diagram?

   please help me.

   thank you very much!

[igorpadykov]

Hi GOPAL

you are right, IPU CSI engine HSYNC,VSYNC timings are edge triggered.

Best regards
igor
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[jhalife]

Thanks. So can i assume, i don't need additional hardware to correct Frame valid/Line valid signal to match VSYNC and HSYNC behavior respectively as shown in Gated clock mode?

[igorpadykov · Accepted solution]

I think you are right.

[jhalife]

thank you for the support