i.MX6 DDR3 pcb routing: Is it neccessary to consider the package pin delays?

[yan2]

Hi,

For DDR4 it is common to consider package pin delays.

What about DDR3 with a i.MX6 SoloX?

Best Regards,

Michael

[igorpadykov]

Hi Schulte

>Is it neccessary to consider the package pin delays?

no. In general they are included in requirements provided in sect.3.5DDR routing rules or

using ibis modelling

IMX6DQ6SDLHDG, Hardware Development Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applic...

Best regards
igor

[yan2]

Hi Igor,

Thanks for response.
That's good to know, but I'm still a little confused.
The Hardware Development Guide recommends to match address and command signals within +/- 25 mils.

Extracting pin package delays from ibis model gives e.g. delays of 45,4 ps for DRAM_ADDR09 and 81,5 ps for DRAM_ADDR13.
Assuming a dielectric constant of 4.8 (which might be lower) for the package this corresponds to bond wire lengths of 244 mil and 439 mil for these two address lines.
A difference of roughly 200 mils.

So the pin package delay is included in recommendation of +/- 25 mil, the overall matching excluding pin package delay would be +/- 225 mils.
Are my considerations understandable?

That would mean e.g. that the pcb trace of DRAM_ADDR09 should actually be 200 mils longer than the pcb trace of DRAM_ADDR13 for superior performance.
Does this makes sense?

Best Regards,
Michael

[igorpadykov · Accepted solution]

>Does this makes sense?

yes. Hardware Development Guide recommendations assume that those delays

could be compensated by DDR Test tool calibration.

In particular below is answer (2014) from packaging group  :
“Freescale typically does not supply the internal trace and bond wire length
information. The IBIS models contain the contribution from the package and
die up to the ball on the bottom of the package, so the internal package
information is not necessary".

Best regards
igor

[yan2]

Hi Igor,

Thank you for your supprt!