i.MX6 DDR3 caliblation: How to calculate the value of DG_DL_ABS_OFFSET0 etc.

[seiichinakano]

Hi community,

I have a question about i.MX6 DDR3 caliblation (ddr_stress_tester_v2.40).

I'd like to calculate the actual delay of

DG_DL_ABS_OFFSET0,WL_DL_ABS_OFFSET0,RD_DL_ABS_OFFSET0 and WR_DL_ABS_OFFSET0.

So,I used ddr_stress_tester_uboot_v2.40 with our custom mx6Q board.

And,I got the following result.

**result**

WL_DL_ABS_OFFSET0:0x23

DG_DL_ABS_OFFSET0:0x334

RD_DL_ABS_OFFSET0:0x5A

WR_DL_ABS_OFFSET0:0x34

************

While,

ARM core speed :1GHz (1.0ns)

DDR_CLK frequency: 528MHz (1.894ns)

When I calculate the value of DG_DL_ABS_OFFSET0 etc. ,

which value should I choose out of 1GHz,528MHz or other frequency ?

According to *"i.MX 6Dual/6Quad Applications Processor Reference Manual,

Rev. 2, 06/2014"(*page 3977).

The following sentence exists.

"The delay of the delay-line would be (DG_DL_ABS_OFFSET0 / 256)* MMDC_CH0

AXI clock (fast clock)."

What is the value of "MMDC_CH0 AXI clock(fast clock) " ?

I think it is 528MHz.

Is this correct or not ?

Likewise,what is the value of "clock period" of "WL_DL_ABS_OFFSET0" ?

Best Regards,

Seiichi Nakano

[Yuri]

Hello,

  Yes, by default it is 528 Mhz. Please use Figure 18-2 ( Clock Tree - Part 1)
of the i.MX6 RM regarding MMDC_CH0_CLK_ROOT and MMDC_CH1_CLK_ROOT.

Have a great day,
Yuri

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[seiichinakano]

Hello yuri

Thank you very much for your answer.

but,I have two additional questions.

((First question))
According to "i.MX 6Dual/6Quad Applications Processor Reference Manual, Rev. 2, 06/2014"(page 3865).
The following sentence exists.

"Under best-case conditions, -40C, 1.21V - 1.6ns."

In this situation(Under best case),
what is the value of  "MMDC_CH0 AXI clock(fast clock) " ?

IF MMDC_CH0 AXI clock equal to 528MHz,
the maximum delay should be about 0.947ns( half cycle of 528MHz).

((Second question))
Is the CLK for "WL_DL_ABS_OFFSET0"  also 528MHz?

In MPWLDECTRL0 field descriptions, I couldn't find "MMDC_CH0 AXI clock(fast clock)" ,only "clock period" exists.

Best Regards,

Seiichi Nakano

[Yuri]

Please refer to i.MX6 DDR3 calibration: How to calculate the value of DG_DL_ABS_OFFSET0 etc.

Regards,

Yuri.

[seiichinakano]

hello

Now I'm going to reply.

************************************

I understood about below.

1.The best-case and worst-case conditions,, relate to internal delays

(gates), and are not frequency dependent.

2."WL_DL_ABS_OFFSET0" is memory clock. Usually it is 528 MHz.

************************************

Thanks you.

2016-03-07 14:24 GMT+09:00 Yuri <admin@community.freescale.com>:

NXP Community

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i.MX6 DDR3 caliblation: How to calculate the value of DG_DL_ABS_OFFSET0

etc.

reply from Yuri Muhin

<https://community.freescale.com/people/Yuri?et=watches.email.thread> in *i.MX

Community* - View the full discussion

<https://community.freescale.com/message/621894?et=watches.email.thread#comment-621894>

[Sadatan123]

Page 3747 of reference manual IMX6DQRM says:

WL_DL_ABS_OFFSET0
Absolute write-leveling delay offset for Byte 0. This field indicates the absolute delay between CK and
write DQS of Byte0 with fractions of a clock period and up to half cycle. This value is process and
frequency independent. The value of the delay can be calculated using the following equation
(WR_DL_ABS_OFFSET1 / 256) * clock period

why here WR_DL_ABS_OFFSET1 is used in formula why not WR_DL_ABS_OFFSET0?