Hi
Below is taken from the i.MX6DQ6SDLHDG (Hardware Development Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors);
Below is taken from the HW_Design_Cheching_List_for_i.MX6DQP6DQ6SDL_Rev3.1.xlsx
One says the constraint is <=25 while the other says +/-50 mils. Which one to trust? With one my design fails and the other it passes..
Regards,
Mete
Solved! Go to Solution.
Just follow the Hardware Development Guide document. Matching the control signals (CS, CKE, ODT) trace length within +/- 50mil margins is enough for normal operation.
Have a great day,
Artur
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Just follow the Hardware Development Guide document. Matching the control signals (CS, CKE, ODT) trace length within +/- 50mil margins is enough for normal operation.
Have a great day,
Artur
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Note: If this post answers your question, please click the Correct Answer button. Thank you!
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Hi Artur,
Thank you very much.
Regards,
Mete