We are developing a custom i.MX6 board based on the NXP SDB, and would like to be able to fit a QUAD, DUAL or DUAL LITE processor depending on the application. There seems to be some disagreement in the documentation regarding the connection of the VDDARM23_IN and VDDARM23_CAP pins when using a DUAL processor. The general consensus seems to be that these should be separated from the VDDARM_IN and VDDARM_CAP nets and grounded for use with a DUAL processor, but this is not universally stated. I suspect that it may be OK to leave them connected as for the QUAD and DL processors, but that optimum power draw may not be achieved in that case.
The reason that this is an issue is that we are basing our board on the SDB layout, and it would be very inconvenient to include the jumper options to separate these nets (as shown in the hardware development guide, IMX6DQ6SDLHDG Rev. 210/2016) on that layout.
I wonder if someone could clarify this question once and for all? I'd also be grateful for clarification of the VDD_CACHE_CAP situation, which seems to be similar.
Hello Ian Dennis,
The official recommendation is as shown on Application Note 4397 (link below), which does state in section 4.1 (Connection differences) that using an i.MX6 Dual you need to connect VDDARM23_IN and VDDARM23_CAP to GDN. Some have opted for leaving them connected as in the Quad variant of the i.MX6 but this will lead to significant current leakage and it’s not the intended configuration of the part, so robust operation cannot be guaranteed.
Common Hardware Design for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite
The SBD layout allows working with the i.MX6DL/D/Q variants by populating different components depending on the processor to be used. The recommendation would be following a similar approach if jumper options are not convenient.
As for VDD_CACHE_CAP, it should be connected to VDDSOC_CAP in both i.MX6 Dual and Quad. There is some more information about this connection also on the same AN4397.
I hope this information helps!
Thanks for your very quick reply.
I don't understand when you say:
"The SBD layout allows working with the i.MX6DL/D/Q variants by populating different components depending on the processor to be used".
Can you tell me which components should be fitted/omitted on the board to connect VDDARM23_IN and VDDARM23_CAP to ground for use with a DUAL processor as you recommend?
Table Common Hardware Design for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Application Note (AN4395) in table 4 shows what different components are required for each configuration. I would also recommend looking at the i.MX6 SABRE schematics for each board, you will see that some components are not placed in certain versions (i.MX6DL, Dual, Quad) of the board while they share the same layout.
I hope this information helps!
Thanks for your reply. I am familiar with the NXP-recommended power connections for the i.MX6 processor variants and the documents you mention, but my question was a specific one: we have laid out our board based on the NXP SDB board (see NXP schematics SPF_27516_C5 for quad, and SPF_ 28857_A2 for quadplus, and the accompanying board layouts, which are essentially the same). We would like to be able to fit Quad, Dual or DualLite processors.
I was wondering whether that layout supports the DUAL processor power recommendations, but I guess I can see that it doesn't since there is no way to ground the VDDARM23_IN and VDDARM23_CAP on that layout. We could add jumpers for this on our board layout, but it looks quite difficult to arrange.
So now I need to ask what exactly would be the consequences of fitting a DUAL processor if we leave the layout with VDDARM23_IN connected to VDDARM_IN an VDDARM23_CAP connected to VDDARM_CAP (as for QUAD and DUALLITE, i.e. not grounded). I understand from the documents that the power consumption would not be 'optimal', but can you tell me how much extra power would be consumed?