i.MX6 CSI, BT.1120, 16-bit mode

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i.MX6 CSI, BT.1120, 16-bit mode

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MarekVasut
Senior Contributor I

Hi,

I'm implementing support for camera input on i.MX6 using mainline Linux 4.3-ish .

I am using an AnalogDevices ADV7181D video encoder, which is connected to the i.MX6Q CSI by using 16bit bus and I have HSync/VSync/PixClk connected. I have an FPGA inbetween, so I can fiddle with the bus wiring if necessary.

The ADV7181D generates 16bit data in YUV422 format, 8bit for Y and 8bit for Cr/Cb , both are transported in single clock tick. The data stream contains EAV/SAV codes. The data stream format from the ADV7181D is interlaced.

I am trying to determine the correct configuration of the CSI and the format of the datastream, so I can capture in 16bit bus mode with deinterlacing in the IPU.

Here is what I tried:

1) If the FPGA is parsing the EAV/SAV codes and generates HSync/Vsync based on them, I can capture in 16bit Non-Gated mode with generic data setting (CSI0_SENS_PRTCL=0x1 ; CSI0_SENS_DATA_FORMAT=0x3 ; CSI0_DATA_WIDTH=0x9). This would be perfect, but the problem is that the i.MX6Q does not have any sort of FRAME input signal, so sometimes the deinterlacing swaps top/bottom frame and the image is slightly distorted. Is there any FRAME input signal which would let the i.MX6 determine which frame is which during deinterlacing ?

2) If the FPGA works in pass-through mode, Hsync/Vsync are not connected AND the i.MX6 CSI is configured in BT1120/Interlaced/SDR, 16bit with generic data setting (CSI0_SENS_PRTCL=0x7 ; CSI0_DATA_WIDTH=0x9), I cannot capture data at all. I tried the following configurations,

but without success, the capture gets stuck:

2.1) Bus mapping: (ADV_D[15:0] <-> MX6_D[19:4]) OR  (ADV_D[15:0] <-> {MX6_D[19:12], MX6_D[9:2]})

2.2) CCIR code configuration:

        CCIR_CODE_3 = 0xff0000 ; CCIR_CODE_2 = 0x0 ; CCIR_CODE_1 = 0x40300 | CCIR_ERR_DET_EN

        OR

        CCIR_CODE_3 = 0xff0000 ; CCIR_CODE_2 = 0xd07df ; CCIR_CODE_1 = 0x40596 | CCIR_ERR_DET_EN

2.3) Sensor data format: CSI0_SENS_DATA_FORMAT=0x3 OR CSI0_SENS_DATA_FORMAT=0x2 OR CSI0_SENS_DATA_FORMAT=0x1

3) If the FPGA works in pass-through mode, Hsync/Vsync are not connected AND the i.MX6 CSI is configured in BT1120/Interlaced/SDR, 8bit with generic data setting (CSI0_SENS_PRTCL=0x7 ; CSI0_SENS_DATA_FORMAT=0x3 ; CSI0_DATA_WIDTH=0x1), I can capture, but the data are missing the Cr/Cb element.

Thus my question, how do I configure the CSI to capture 16bit BT1120 data with embedded EAV/SAV codes using the CSI ?

What shall be the format of EAV/SAV codes on the CSI bus when operating in 16bit mode, shall they be on the MSB of the bus only or shall they be on both MSB and LSB? I would like to understand in detail how the decoding of these AV codes work, so I can tweak the FPGA configuration to feed the i.MX6 the correct stuff.

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philippzabel
Contributor I

Are you using the the ADV7181D's 16-bit SDR mode with Y7-0 on pins P19-12 (connected to CSI0_DATA19-12) and Cb/Cr7-0 on pins P9-2 (connected to CSI0_DATA11-4)? Pins P11-10 are high impedance in this mode.

ITU-R BT.1120-8 assumes a 10-bit wide transport with the LSB set to zero for 8-bit video data, so I *assume* the codes need to be in the MSB only and at least the next two lower input pins shall be low during SAV/EAV.

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MarekVasut
Senior Contributor I

> Are you using the the ADV7181D's 16-bit SDR mode with Y7-0 on pins P19-12 (connected to CSI0_DATA19-12) and Cb/Cr7-0 on

> pins P9-2 (connected to CSI0_DATA11-4)? Pins P11-10 are high impedance in this mode.

I tested both options according to [1] page 30. I didn't observe much impact other than slightly distorted colors. And this only worked in 8bit CSI mode.

[1] A Deep Dive into Image Processing for i.MX 6 Series Applications Processors

> ITU-R BT.1120-8 assumes a 10-bit wide transport with the LSB set to zero for 8-bit video data, so I *assume* the codes need to be

> in the MSB only and at least the next two lower input pins shall be low during SAV/EAV.

Right now, I am duplicating the codes between LSB and MSB. Do you think it makes sense to scrub the colors from the LSB and just hold LSB zero or does the CSI not care about what's in LSB when the codes are transferred?

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qiang_li-mpu_se
NXP Employee
NXP Employee

Hi Marek, you can't make BT1120 16bits mode and gated clock 16bits mode working on the same board. They used different data pins. And we have verified both of them.

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MarekVasut
Senior Contributor I

Yes I can. Like I mentioned in the original text, I have an FPGA between the ADV7181D and the i.MX6, so I can fiddle with the signals as needed ; I can generate HS/VS/F signals from the EAV/SAV codes, I can change the routing of the signals ... the only thing I cannot do is I cannot do deinterlacing in the FPGA (conversion from interlaced to progressive).

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qiang_li-mpu_se
NXP Employee
NXP Employee

Hi Marek, that's OK since you can control all data lines as you wanted.

From your dumped register setting, "CSI_SENS_FRM_SIZE: 023f02cf", It is not correct. It should be the full video size with blank data, for PAL, it is 720*625.

"CSI_ACT_FRM_SIZE:  023f02cf" is correct, it is the active video size, 720*576 for PAL.

By the way, please also dump your IDMAC 0 setting, reference to function _ipu_ch_param_dump() of file linux-kernel\drivers\mxc\ipu3\ipu_param_mem.h.

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MarekVasut
Senior Contributor I

> From your dumped register setting, "CSI_SENS_FRM_SIZE: 023f02cf", It is not correct. It should be the full video size with blank

> data, for PAL, it is 720*625. "CSI_ACT_FRM_SIZE:  023f02cf" is correct, it is the active video size, 720*576 for PAL.

As I mentioned in the initial text, I am using interlaced mode, so I need to use half of the frame there.

In fact, I managed to solve my issue by tweaking CPMEM configuration and I am now testing the solution.

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qiang_li-mpu_se
NXP Employee
NXP Employee

No, for interlaced input, you still can set frame size in CSI registers and  CPMEM, then the IPU can receive the two fields data into one frame data, line skip line.

If you set field size in CSI registers and  CPMEM, there will be issue to identify ODD and EVEN fields.

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Marek

>3) If the FPGA works in pass-through mode, Hsync/Vsync are not connected AND the i.MX6 CSI is

>configured in BT1120/Interlaced/SDR, 8bit with generic data setting (CSI0_SENS_PRTCL=0x7 ;

>CSI0_SENS_DATA_FORMAT=0x3 ; CSI0_DATA_WIDTH=0x1), I can capture, but the data are missing the Cr/Cb element

CSI0_SENS_DATA_FORMAT=0x3 - Bayer or Generic data

for capturing Cr/Cb it should be :

001 YUV422 (YUYV...) or

010 YUV422 (UYVY...)

> If I operate the CSI in BT1120 mode, I must configure the CSI to 8bit mode, even if my input data are 16bit in total ?

CSI0_DATA_WIDTH is width per colour component, so in BT1120 16 bits mode with

EAV and SAV data embedded, it should be =0001 8 bits per color and data arrives

on MX6_D[19:12], MX6_D[9:2]}.

[1] page 30 just reproduces  Table 66. Camera Input Signal Cross Reference, Format, and Bits Per Cycle

http://cache.freescale.com/files/32bit/doc/data_sheet/IMX6DQCEC.pdf

option with data on MX6_D[19:4]) - is (footnote 6)

YCbCr, 16 bits—Supported as a “generic-data” input—with no on-the-fly processing.

CSI0_SENS_DATA_FORMAT=0x3 and there are no colour components

Best regards

igor

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765077233
Contributor I

Hi igorpadykov

Now our sensor's hardware communicating to IMX6DL CSI port is by MX6_D[19:4],also has HSYNC/VSYNC/PCLK signal.And sensor output format is YUV422. I would like to know what should I configure my sensor driver,especially pixelformat and if_type in function ioctl_g_ifparm().Could you provide some similar patch?

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qiang_li-mpu_se
NXP Employee
NXP Employee

For your case, MX6_D[19:4,HSYNC/VSYNC/PCLK, YUV422, you should set CSI_DATA_WIDTH to 16 bits per color, and CSI_SENS_DATA_FORMAT to Bayer or Generic data.

It is same as RGB565 on 16bits CSI, the reference patch: https://community.nxp.com/docs/DOC-97981

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765077233
Contributor I

hi Qiang Li:

Now I can get the sensor image by executing mxc_v4l2_capture,the image is attached .And I read CSI_DATA_WIDTH,it's 16 bits per color;

And CSI_SENS_DATA_FORMAT  is generic data.But in the image'capture_image.bmps left and top side,there are black edge.Could you provide some advise kindly?

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qiang_li-mpu_se
NXP Employee
NXP Employee

You can skip them by setting the register IPU_CSIx_OUT_FRM_CTRL.

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qiang_li-mpu_se
NXP Employee
NXP Employee

For BT1120 16 bits mode, there should be EAV and SAV data embedded, only 16 data lines and 1 pixel clock line was needed.

Hardware link on iMX6 CSI data line: CSI_D_19 ~ CSI_D_12, CSI_D9 ~ CSI_D_2; (The U/V and EAV/SAV data are transfered on 8 bits MSB, CSI_D_19 ~ CSI_D_12, the Y data is transfered on 8 bits LSB, CSI_D9 ~ CSI_D_2)

IPU_CSI_SENS_CONF register setting:

     CSI_EXT_VSYNC should be 0b0 for Internal VSYNC mode.

     CSI_DATA_WIDTH should be 0b0001 for 8 bits per color, it means each Y/U/V is 8 bits.

     CSI_SENS_DATA_FORMAT should be 0x010, YUV422 UYVY.

     CSI_SENS_PRTCL should be 0b111, BT.1120 SDR mode.

For CCIR_CODE registers setting, if the EAV/SAV of input signal follows PAL signal:

   /* PAL case */

   /*

    * Field0BlankEnd = 0x6, Field0BlankStart = 0x2,

    * Field0ActiveEnd = 0x4, Field0ActiveStart = 0

    */

   __raw_writel(0x40596, CSI_CCIR_CODE_1(csi));

   /*

    * Field1BlankEnd = 0x7, Field1BlankStart = 0x3,

    * Field1ActiveEnd = 0x5, Field1ActiveStart = 0x1

    */

   __raw_writel(0xD07DF, CSI_CCIR_CODE_2(csi));

   __raw_writel(0xFF0000, CSI_CCIR_CODE_3(csi));

If the EAV/SAV of input signal follows NTSC signal:

   /* NTSC case */

   /*

    * Field0BlankEnd = 0x7, Field0BlankStart = 0x3,

    * Field0ActiveEnd = 0x5, Field0ActiveStart = 0x1

    */

   __raw_writel(0xD07DF, CSI_CCIR_CODE_1(csi));

   /*

    * Field1BlankEnd = 0x6, Field1BlankStart = 0x2,

    * Field1ActiveEnd = 0x4, Field1ActiveStart = 0

    */

   __raw_writel(0x40596, CSI_CCIR_CODE_2(csi));

   __raw_writel(0xFF0000, CSI_CCIR_CODE_3(csi));

On iMX53 platform,  we already have the verified working sample code: Patch to support adv7180 TVin chip for Freescale Android R10.4 BSP on iMX53 -blog archive

The IPU setting is same for BT1120 16 bits input on iMX53 and iMX6.

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MarekVasut
Senior Contributor I

Yeah, that was also one of the combinations I tested, see above, but this does not work. I am missing the Cr/Cb element if I configure the CSI in 8bit data mode (CSI_DATA_WIDTH=0x1) . Any idea what else should I check? Why shouldn't the CSI be configured in 16bit data mode (CSI_DATA_WIDTH=0x9) instead ?

Also, can you please answer my other questions ?

Thanks

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qiang_li-mpu_se
NXP Employee
NXP Employee

No, CSI_DATA_WIDTH must be 0x1, in BT1120 mode, this WIDTH means bits of each Y/U/V.

Please dump your CSI registers setting for review, and please also dump your IDMAC setting for review. (To dump the IDMAC setting, you can open the debug messages in function _ipu_ch_param_dump() of file "linux\drivers\mxc\ipu3\ipu_param_mem.h").

For CCIR code, it aligns with EAV/SAV data, for example FF 00 00 XX, the first 3 bytes FF0000 are fixed, they should be filled into CCIR_CODE_3 register:

     __raw_writel(0xFF0000, CSI_CCIR_CODE_3(csi));

The last byte XX is the F,V,H data for interlaced signal, for example PAL signal:

Field 0 - First Vertical Blanking(Top)

     EAV Code 0xFF0000B6, F=0,V=1,H=1, in CCIR_CODE_1 register, CSI_END_FLD0_BLNK_1ST (3 bits data is H,V,F) should be 0b110, in BSP code Field0BlankEnd = 0x6.

     SAV Code 0xFF0000AB, F=0,V=1,H=0, in CCIR_CODE_1 register, CSI_STRT_FLD0_BLNK_1ST (3 bits data is H,V,F) should be 0b010, in BSP code Field0BlankStart = 0x2.

Field 0 - Active Video
     EAV Code 0xFF00009D, F=0,V=0,H=1, in CCIR_CODE_1 register, CSI_END_FLD0_ACTV (3 bits data is H,V,F) should be 0b100, in BSP code Field0ActiveEnd = 0x4.

     SAV Code 0xFF000080, F=0,V=0,H=0, in CCIR_CODE_1 register, CSI_STRT_FLD0_ACTV (3 bits data is H,V,F) should be 0b000, in BSP code Field0ActiveStart = 0x0.

Field 0 - Second Vertical Blanking(Bottom)

     EAV Code 0xFF0000B6, F=0,V=1,H=1, in CCIR_CODE_1 register, CSI_END_FLD0_BLNK_2ND (3 bits data is H,V,F) should be 0b110, in BSP code Field0BlankEnd = 0x6.

     SAV Code 0xFF0000AB, F=0,V=1,H=0, in CCIR_CODE_1 register, CSI_STRT_FLD0_BLNK_2ND (3 bits data is H,V,F) should be 0b010, in BSP code Field0BlankStart = 0x2.

So CCIR_CODE_1 register is:

     __raw_writel(0x40596, CSI_CCIR_CODE_1(csi));

The CCIR_CODE_2 register is for Field 1 data.

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MarekVasut
Senior Contributor I

> No, CSI_DATA_WIDTH must be 0x1, in BT1120 mode, this WIDTH means bits of each Y/U/V.

Just so I understand it correctly.

- If I operate the CSI in Gated mode, I configure the width the 16bit and I am getting correct data.

- If I operate the CSI in BT1120 mode, I must configure the CSI to 8bit mode, even if my input data are 16bit in total ?

> Please dump your CSI registers setting for review, and please also dump your IDMAC setting for review. (To dump the IDMAC

> setting, you can open the debug messages in function _ipu_ch_param_dump() of file "linux\drivers\mxc\ipu3\ipu_param_mem.h").

I am not using the freescale-provided kernel sources, but see below:

imx-ipuv3 2400000.ipu: IPU_CONF =       0x00000000

imx-ipuv3 2400000.ipu: IDMAC_CONF =     0x0000002F

imx-ipuv3 2400000.ipu: IDMAC_CHA_EN1 =  0x00000000

imx-ipuv3 2400000.ipu: IDMAC_CHA_EN2 =  0x00000000

imx-ipuv3 2400000.ipu: IDMAC_CHA_PRI1 =         0x00000001

imx-ipuv3 2400000.ipu: IDMAC_CHA_PRI2 =         0x00000000

imx-ipuv3 2400000.ipu: IDMAC_BAND_EN1 =         0x00000000

imx-ipuv3 2400000.ipu: IDMAC_BAND_EN2 =         0x00000000

imx-ipuv3 2400000.ipu: IPU_CHA_DB_MODE_SEL0 =   0x00000000

imx-ipuv3 2400000.ipu: IPU_CHA_DB_MODE_SEL1 =   0x00000000

imx-ipuv3 2400000.ipu: IPU_FS_PROC_FLOW1 =      0x00000000

imx-ipuv3 2400000.ipu: IPU_FS_PROC_FLOW2 =      0x00000000

imx-ipuv3 2400000.ipu: IPU_FS_PROC_FLOW3 =      0x00000000

imx-ipuv3 2400000.ipu: IPU_FS_DISP_FLOW1 =      0x00000000

imx-ipuv3 2400000.ipu: IPU_INT_CTRL(0) =        10800000

imx-ipuv3 2400000.ipu: IPU_INT_CTRL(1) =        00000000

imx-ipuv3 2400000.ipu: IPU_INT_CTRL(2) =        00000001

imx-ipuv3 2400000.ipu: IPU_INT_CTRL(3) =        00000000

imx-ipuv3 2400000.ipu: IPU_INT_CTRL(4) =        00000000

imx-ipuv3 2400000.ipu: IPU_INT_CTRL(5) =        00000000

imx-ipuv3 2400000.ipu: IPU_INT_CTRL(6) =        00000000

imx-ipuv3 2400000.ipu: IPU_INT_CTRL(7) =        00000000

imx-ipuv3 2400000.ipu: IPU_INT_CTRL(8) =        00000000

imx-ipuv3 2400000.ipu: IPU_INT_CTRL(9) =        00000000

imx-ipuv3 2400000.ipu: IPU_INT_CTRL(10) =       00000000

imx-ipuv3 2400000.ipu: IPU_INT_CTRL(11) =       00000000

imx-ipuv3 2400000.ipu: IPU_INT_CTRL(12) =       00000000

imx-ipuv3 2400000.ipu: IPU_INT_CTRL(13) =       00000000

imx-ipuv3 2400000.ipu: IPU_INT_CTRL(14) =       00000208

imx-ipuv3 2400000.ipu: CSI_SENS_CONF:     04000a70

imx-ipuv3 2400000.ipu: CSI_SENS_FRM_SIZE: 023f02cf

imx-ipuv3 2400000.ipu: CSI_ACT_FRM_SIZE:  023f02cf

imx-ipuv3 2400000.ipu: CSI_OUT_FRM_CTRL:  00000000

imx-ipuv3 2400000.ipu: CSI_TST_CTRL:      00000000

imx-ipuv3 2400000.ipu: CSI_CCIR_CODE_1:   01040596

imx-ipuv3 2400000.ipu: CSI_CCIR_CODE_2:   000d07df

imx-ipuv3 2400000.ipu: CSI_CCIR_CODE_3:   00ff0000

imx-ipuv3 2400000.ipu: CSI_MIPI_DI:       ffffffff

imx-ipuv3 2400000.ipu: CSI_SKIP:          00000000

Can you please answer my question about the gated mode ? Is there some FRAME input signal into the CSI ?

Also, I understand how the EAV/SAV codes work, I would like to know how they should look on the 16bit bus. But I think Philipp kinda confirmed my expectation.

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