i.MX6 ASRC clock divider calculations

[abelal]

Hi,

While looking at the i.MX6 manual (Rev. 1, 04/2013) at the start of page 655, the manual says "The clocks have the following restriction. If the prescaler is set to 1, the clock divider can only be set to 1 and the clock source must have a 50% duty cycle.". Now, if we look at the Freescale BSP the clock divider calculations for ASRC (get_clock_divider()) do not seem to take care of this fact and in case the prescaler is calculated as 0 the divider is set to 'ra - 1'. Is this a bug in the BSP or does the manual need updating? because I think they are contradicting. Kindly comment.

BR,

Awais

[weidong_sun]

Hello, Awais,

       I agree with you!  From Reference manual, linux bsp should consider this conditions, but I can't confirm if it is a bsp bug, it should be done by R&D team. If you find issue duiring debuging or testing, you can adjust corresponding code.

Regards,

Weidong

[abelal]

Hi Weidong,

Can you please elaborate a little on why does the manual warn against this situation and what are the consequences?

BR,

Awais

[weidong_sun]

Hi Awais,

     Did you meet some issues about this part during your application?

Regards,

Weidong