i.MX537 (Karo TX53-8130) U-Boot Splash Screen on 1024x768 LVDS display.

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i.MX537 (Karo TX53-8130) U-Boot Splash Screen on 1024x768 LVDS display.

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jjkropp-Triton
Contributor II

Hi.

U-Boot is running the pixel clock at 85 MHz when it's up to run at 65 MHz.  This version of U-Boot for the TX53 is using the ipu video drivers files located in /drivers/video/.

Has anyone seen a fix for this type of problem in U-Boot?

I think the DI_BS_CLKGEN0 and DI_BS_CLKGEN1 registers are being loaded with the wrong values,  or the clk->parent->rate is wrong.  Thanks for any help...

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jjkropp-Triton
Contributor II

igor,

Thanks so much for your response.

I fixed my problem by setting adding  "setup_pll PLL4_BASE_ADDR, 455"  to the lowlevel_init.s file located in  /arch/arm/cpu/armv7/mx5/ folder.  Apparently Karo did not set this properly with the CONFIG_TX53 switch in the file.  They placed the PLL setup under the "#ifndef CONFIG_TX53" case.  I'm sending a help request to Karo to confirm this. 

Karo does support the Freescale 10.1"  LVDS panel on their development board, and I'm guessing it would have the same issue.

Hopefully this will help someone else in the future.

Thanks again,

Jed

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jjkropp-Triton
Contributor II

Confirmed by Karo.

Currently U-Boot for TX53 has no way to set the clock rate of the Video PLL at runtime.

So your change is currently the only way to select a different clock rate than the default 85MHz.

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Jed

one can verify clock and other lcd settings using obds (ipu_test.c)

Lab and Test Software (2)

On-Board Diagnostic Suit for the i.MX53 Quick Start Board (REV 2011.39)

http://www.nxp.com/products/power-management/pmics/pmics-for-i.mx-processors/i.mx53-quick-start-boar...

also splash screen is supported in nxp bsp for i.MX53 (on the same link), refer to attached document

sect.5.5 Splash screen support

Board Support Packages (8)

Linux 2.6.35 Source Code Files and documentation 11.09. Supports MCIMX53-START and MCIMX53-START-R

General steps for connecting new lvds panel are provided in Chapter 18 Connecting an LVDS Panel,

Table 17-2. Timing Parameters i.MX53 System Development User’s Guide

http://www.freescale.com/files/32bit/doc/user_guide/MX53UG.pdf

Best regards

igor

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jjkropp-Triton
Contributor II

igor,

Thanks so much for your response.

I fixed my problem by setting adding  "setup_pll PLL4_BASE_ADDR, 455"  to the lowlevel_init.s file located in  /arch/arm/cpu/armv7/mx5/ folder.  Apparently Karo did not set this properly with the CONFIG_TX53 switch in the file.  They placed the PLL setup under the "#ifndef CONFIG_TX53" case.  I'm sending a help request to Karo to confirm this. 

Karo does support the Freescale 10.1"  LVDS panel on their development board, and I'm guessing it would have the same issue.

Hopefully this will help someone else in the future.

Thanks again,

Jed

View solution in original post

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