i.MX53 DDR2 calibration and DRAM_SDWE drift

[torus1000]

Hi Chip experts,

In spite of DDR2 calibration applied, LCD screen unstable occured immediately after bootup.
It seems DDR2 write was OK but failed at read&write.
5 min after bootup, LCD screen looked quite stable.

So I checked difference and found low output of DRAM_SDWE slightly higher around 400mV againt 200mV@5min have passed.

(Q) What's the reason of DRAM_SDWE level drifted?

(Q) Is it possible to enhance ZQ during bootup in order to avoid screen unstable?

Can anyone help me?

Best Regards.

[igorpadykov]

Hi torus1000

1.voltage levels can be found in IMX53CEC Table 13. DDR2 I/O DC Electrical Parameters

reason may be some load (may be ddr chip is broken) on that line which draws current,

changing with temperature.

One can try to increase its drive strength using register IOMUXC_SW_PAD_CTL_GRP_CTLDS

2. I doubt that this may help, though one can try. Better option is to run ddr test and check memory

DDR_STRESS_TESTER_FOR_MX51_MX53

ESDCTL boot parameters can be set in uboot flash_header.S

Best regards

igor

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[torus1000]

Dear Igor,

Thank you for replying.

We already tried max drive strength but result looked still unstable.

So we will try next to change ESDCTL_SDCTRL for more/less delay on SDCLK.

(Q1) Does more delay improve timing margin to the CS/RAS/CAS/WE/<adr>/<dat> of DDR2 read?

Regard to the following description: "Add sdclk0 delay of 1 delay units.";

(Q2) How long [pSec] does 1 delay units mean?

When we write 0x00000300(SDclk0_del=2'b11) to the ESDCTL_SDCTRL with JTAG-ICE,

but read value was 0x00018000.

(Q3) What was wrong with my writing?

Best regards.

[igorpadykov · Accepted solution]

Hi torus1000

as these are new questions, I would suggest to

create new thread for them

Thanks and Best regards

igor

[torus1000]

Dear Igor

Sure. I created a new thread. Please have a look.

     here: https://community.freescale.com/message/534603#534603

BR