i.MX51 disable interrupts

キャンセル
次の結果を表示 
表示  限定  | 次の代わりに検索 
もしかして: 

i.MX51 disable interrupts

ソリューションへジャンプ
747件の閲覧回数
george
Senior Contributor II

Hi all,

Please let me know about interruption of i.MX51.

When disabling interrupts, should I-bit of the CPSR register of ARM core be set to DISABLE?

Or is anything alse needed?

GPIO interrupt occurs I-bit in set to DISABLE.

* Trust Zone Interrupt Contoller is ENABLE and F-bit of CPSR register are ENABLE.

Please give some ideas.

Best Regards,

George

ラベル(1)
0 件の賞賛
1 解決策
579件の閲覧回数
jimmychan
NXP TechSupport
NXP TechSupport

I think you can try to configure the interrupt control register (INTCTRL) of TZIC. According to the Chapter 57.3.3.2, INTCTRL

can enable or disable all normal or secure interrupts to the CPU. For more details, please read the i.MX51 Reference Manual (i.MX51RM) Chapter 57.3.3.2.

元の投稿で解決策を見る

0 件の賞賛
1 返信
580件の閲覧回数
jimmychan
NXP TechSupport
NXP TechSupport

I think you can try to configure the interrupt control register (INTCTRL) of TZIC. According to the Chapter 57.3.3.2, INTCTRL

can enable or disable all normal or secure interrupts to the CPU. For more details, please read the i.MX51 Reference Manual (i.MX51RM) Chapter 57.3.3.2.

0 件の賞賛