i.MX51 disable interrupts

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i.MX51 disable interrupts

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george
Senior Contributor II

Hi all,

Please let me know about interruption of i.MX51.

When disabling interrupts, should I-bit of the CPSR register of ARM core be set to DISABLE?

Or is anything alse needed?

GPIO interrupt occurs I-bit in set to DISABLE.

* Trust Zone Interrupt Contoller is ENABLE and F-bit of CPSR register are ENABLE.

Please give some ideas.

Best Regards,

George

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jimmychan
NXP TechSupport
NXP TechSupport

I think you can try to configure the interrupt control register (INTCTRL) of TZIC. According to the Chapter 57.3.3.2, INTCTRL

can enable or disable all normal or secure interrupts to the CPU. For more details, please read the i.MX51 Reference Manual (i.MX51RM) Chapter 57.3.3.2.

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jimmychan
NXP TechSupport
NXP TechSupport

I think you can try to configure the interrupt control register (INTCTRL) of TZIC. According to the Chapter 57.3.3.2, INTCTRL

can enable or disable all normal or secure interrupts to the CPU. For more details, please read the i.MX51 Reference Manual (i.MX51RM) Chapter 57.3.3.2.

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