i.MX502 power-up sequence

[norishinozaki]

Hello,

I'm creating i.MX502 power-up sequence by referring to SDG and the EVK schematics.

I found 3.15V including VDD3P0 is supplied by DC/DC, not by MC34708.

Then it looks the DC/DC is enable by GPIO after the CPU core startups.

Is this correct?

In the case, the VDD3P0 is almost the last to be enabled

Are VDD2P5, VDD1P8, VDD1P2 Ok to be enabled before VDD3P0?

Best regards,

Nori Shinozaki

[igorpadykov]

Hi Nori

some clarification is given at footnote 2

to IMX50CEC sect.4.2.1 Power-Up Sequence

2). No power-up sequence dependencies exist between the supplies shown

shaded in gray.

However VDD2P5, VDD1P8, VDD1P2 should be enabled after VDD3P0

as shows Figure 2

Note there may be discrepancies between reference design and datasheet

descriptions since reference design is created before datasheet specs

are finalized.

Best regards

igor

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[norishinozaki]

Hello Igor,

I'm concerned on the following VDDs, not on the shaded ones

In the EVK, VDD2P5, 1P8, 1P2 are enabled prior to VDD3P0.

Regards,

Nori Shinozaki

[igorpadykov · Accepted solution]

Hi Nori

VDD2P5, VDD1P8, VDD1P2 should be enabled after VDD3P0

as shows Figure 2

Note there may be discrepancies between reference design and datasheet

descriptions since reference design is created before datasheet specs

are finalized.

Best regards

igor

[norishinozaki]

Igor,

I see, thank you!

Best regards,

Nori Shinozaki