i.MX287:cpu address is overlapped between On-chip ram and peripheral

[hwo]

Hi all,

       Recent days, I come across a situation: there's a decoder, such as SN74LVC138APWR(3-input, 8-output), which uses cpu address pins(A6, A5, A4) as the input signals and LCD_RD_E(LCD pin) as cs signal. Doesn't have any LCD devices on the board. So the question is how can I obtain one of the eight output of decoder.

My thought is activating the LCD_RD_E pin, then write data to the A6A5A4 address and leave all the other cpu address pins to ZERO. However this address must be overlapped with on-chip ram.

So is it right to have the decoder connected like this or how can I arrange the address?

Thanks in advance!

[igorpadykov]

Hi h

if you are speaking about EMI_A00...pins then

address of External Memory EMI is 0x40000000 according to

Table 4-1. Address Map for i.MX28 i.MX28 Reference Manual (rev.1, 9/2010)

http://cache.freescale.com/files/dsp/doc/ref_manual/MCIMX28RM.pdf

Addresses of other modules also are shown on that table.

One can put data on decoder using processor pins as GPIOs, check Chapter 9 RM.

Best regards

igor

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[hwo]

Thank you igor.

It's better to use GPIO as the input pins of decoder.

  I am a little confused about the cpu pins. According to the iMX28RM.pdf, I don't see the cpu address pins except some named by functional name such as EMI pins, LCD pins, etc.

So I want to know is it possible to have cpu address pins as the input of decoder. And where's the cpu address pins?

Thank you again!

[igorpadykov]

pelase read Chapter 9 Pin Control and GPIO (PinCtrl) iMX28RM.pdf,

in description you can find address.

~igor