(i.MX28) How can we improve the waveforms of EMI?

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(i.MX28) How can we improve the waveforms of EMI?

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hikaruuruno
Contributor III

Hi Community,

We are having a problem with the waveforms of EMI of i.MX28.
There are overshoots/undershoots which are more than 300mV on Address/Command signals.
The image is A6 probed at a via near DDR2.

A6.png

Are there any way to reduce the shoots from Address/Command without modifying hardware?

The conditions of our board are as follows:
-The board is 6-layer.
-The pattern length of each EMI line is 30.2-34.0mm.
-There are no dumping resistors on the Address/Command line.
-The only register settings which is modified from the reset value is bit 1 of EMRS(1), or HW_DRAM_CTL183. (Reducing the drive strength of DDR2.)
-Adding dumping registers to the Address/Command lines are too risky.

The board is our original design and the pattern of EMI is not copied from EVK since our board is too small to do so.
Instead we simulated the pattern before manufacturing the board and the result was that the overshoots and undershoots are less than 300mV.
Since the vias we used to probe were a little apart from the balls of DDR2, the shoots are not as bad as it seems at the balls.
But as there is no way to observe the exact waveform at the ball, we'd like to improve the waveform we can see.

Thank you,
Hikaru

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art
NXP Employee
NXP Employee

Try to play with the ODT and drive strength settings of the i.MX28 EMI signals

in the HW_PINCTRL_EMI_ODT_CTRL and HW_PINCTRL_EMI_DS_CTRL registers of the

i.MX28 Pin Control (PINCTRL) module.


Have a great day,
Artur

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art
NXP Employee
NXP Employee

Try to play with the ODT and drive strength settings of the i.MX28 EMI signals

in the HW_PINCTRL_EMI_ODT_CTRL and HW_PINCTRL_EMI_DS_CTRL registers of the

i.MX28 Pin Control (PINCTRL) module.


Have a great day,
Artur

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Note: If this post answers your question, please click the Correct Answer button. Thank you!
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868 Views
hikaruuruno
Contributor III

Hi Artur,

Thank you for your reply.

Since the reset value of the drive strength is the lowest, I don't think changing the setting reduces the shoot.

As for the ODT, I thought the ODT is used when there are 2 or more RAMs...

Is there any settings you recommend, or should we find the optimum setting by trial and error?

Thank you,

Hikaru

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art
NXP Employee
NXP Employee

The issue is very design dependent, so, no strict recommendations can be done. Just try to play with the settings.

Best Regards,

Artur

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hikaruuruno
Contributor III

Hi Artur,

Thank you for the advice.

We will try ODT.

Best regards,

Hikaru

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hikaruuruno
Contributor III

Hi Artur,

By enabling the ODT, we could reduce the undershoots on the address/command signals.

However the worst value of the shoots still exceed 300mV, it's less than 500mV now.

In our case, the results of TLOAD 50 ohm and 75 ohm was almost same. Both cases resulted in reduced undershoots. ODT calibration didn't make significant difference.

Best regards,

Hikaru Uruno

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