i.MX25 CPU .The source of MODULE CLOCK for I2C and UART is what?

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i.MX25 CPU .The source of MODULE CLOCK for I2C and UART is what?

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sunsun
Contributor I

Hello !

i.MX25 CPU

I want to know the “MODULE CLOCK” for I2C and UART is what?

The source of the “MODULE CLOCK” is where?

How to config the frequency of the "MODULE CLOCK"  ?

Wish your help。

Thanks!

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Sun

one can look on sect.15.3.3.4 Clock Gating Control Register 0 (CGCR0),
Table 15-15. PER Clock Distribution i.MX25 Multimedia Applications Processor Reference Manual

Best regards
igor
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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Sun

one can look on sect.15.3.3.4 Clock Gating Control Register 0 (CGCR0),
Table 15-15. PER Clock Distribution i.MX25 Multimedia Applications Processor Reference Manual

Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
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sunsun
Contributor I

Thanks you,but I also do not understand。

15.3.3.4 show the “PER Clock Gating” and the “AHB Clock Gating”,like to the PER Clock Gating 【6】,witch is the ipg_per_i2c clock ,but I do not think it is the module clock for I2C module。

Because  【Table 29-6. I2C Frequency Register Field Descriptions】show 【The serial bit clock frequency is equal to Module Clock divided by the divider shown in Table 29-7.】。

Module Clock = PER clock ?

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igorpadykov
NXP TechSupport
NXP TechSupport

>Module Clock = PER clock ?

yes

pastedImage_1.jpg

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sunsun
Contributor I

Thank you!

But how to understand this :

“46.4.2.1 Clock requirements.

UART module receives 2 clocks, peripheral_clock and module_clock. The peripheral_clock is used as
write clock of the TxFIFO, read clock of the RxFIFO and synchronization of the modem control input pins.
It must always be running when UART is enabled. There is an exception in stop mode (see
Section 46.4.2.3, “Clocking in Low-Power Modes”).
The module_clock is for all the state machines, writing RxFIFO, reading TxFIFO, etc. It must always be
running when UART is sending or receiving characters.This clock is used in order to allow frequency
scaling on peripheral_clock without changing configuration of baud rate (module_clock staying at a fixed
frequency).
The constraints on peripheral_clock and module_clock are as follows:
• peripheral_clock and module_clock can totally be asynchronous. Off course, they can also be
synchronous.
• Due to the 16x oversampling of the incoming characters, module_clock frequency must always be
greater or equal to 16x the maximum baud rate. For example, if max baud rate is 4 Mbit/s,
module_clock must be greater or equal to 4 M x 16 = 64MHz.”

Is not peripheral clock = PER Clock?

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igorpadykov
NXP TechSupport
NXP TechSupport

here "peripheral_clock" = ipg_clk_x

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sunsun
Contributor I

Can you tall me what is the source of SDCLK?

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