i.MX23 and DDR SDRAM routing

[danix]

Hey all,

I'm designing a custom board with i.MX23 and micron DDR as in the EVK reference schematic from freescale...

I routed all the high speed signals (D00-D15, DQM[1..0], DQS[1..0], clk and clkn) only on bottom and top and matched the number of vias i used as in the application note, but my worry is that to what extent

is matching the trace length acceptable. In my design the longest trace is 27mm  (which is physically impossible to decrease in my layout). should all the rest be strictly matched or what tolerance is acceptable (I have traces as short as 21mm)?

I'm just waiting a response to continue,

thanks

[ManuMartinez]

Well, I've managed to boot a kernel :-). The DDR routing worked fine.

But on the other hand I've had a lot of problems with the nand (I didn't put a SD/MMC port). I used a Hynix's H5DU5162GTR. With the first boards after flashing the nand few times (30-50) the kernel found some "bad eraseblock" errors and later the nand stopped working.  My collegue, who is working with the software, has had to decrease the access timming to the nand and now all seems to work well. I've read several comments of people who have had problems with nand chips using iMX233 and iMX28x: now I understand why the EVKs include a nand socket to test different chips...

We've purchased a iMX28 EVK. My collegue has customized the BSP, installed QT and SocketCAN, and so on. Now is my turn to design a custom board XD.

Cheers.

[ManuMartinez]

Finally I've finished my proto. I've reached to match all DDR nets (data, address and control) between 25mm and 30mm, all of them with 2 vias. Also I've improved the GND plane and I've placed a solid 2.5V plane and an island for Vref. As an extra I've placed the chassis ground ring in the border.


I still worried by the manufacturability of mx233 in 2L since it's impossible to meet DDR length requeriments and create an interrupted ground plane at same  time. So this is my last attempt: if it doesn't work I'll change to 4L :-).


Thanks David and Felix.

[DaviddeBethel]

Hi again,

 Certainly it is good practice to ensure that there is the same number of vias on all nets.  This is something I try to apply to just about all signal lines regardless of speed (it helps me think about minimising vias!). 

I didnt worry about terminating resistors, just went for matched lengths and good ground planes.

I will be amazed if you can meet these requirements only on a two layer board.  It probably isnt impossible but it sure as hell is not going to be easy.

Best of luck

David

[ManuMartinez]

Thanks David,

Sorry: I meant oxidising. Anyway, I have many mistakes in my prototype regarding with the power planes and the number of vias in the data lines.... since those should be the same on each net and I have some nets with 2 vias and others without any. So I have to design another board and to change of manufacturer or try with another finished (now is chemical silver). By now I'm trying to delay the oxidising using a lacquer.

What really worries me now is if I should to use termination resistors or not. Using only two layers is very difficult to accomplish the goal of less than 22.5mm specified on the pcb guidelines.

Manu.

[DaviddeBethel]

Hi,

From my experience I would be worried about vias 'rusting'! I assume you mean oxidising, and if the vias have been plated properly this shouldn't happen and yes, if they are oxidising it will change the impedance and probably result in eventual open circuit.  You should talk to your manufacturer.

David

[ManuMartinez]

Hello,

I'm having some problems with my first design using imx233 in 2L-QFP. When I assembly a board it works right but few days later the system stops working: I can see a DRAM fail code in the console and the system goes to a non-stop reset after detec 5V.

I've tried to make them work again by replacing the imx233, the RAM and the Flash but I get the same behaviour. My manufacturer  is quite cheap but I have to recognize that the quality is a bit poor: I can see how the soldermask loses color and the vias rusts after few days. So I guess that simply the impedance of some of the nets change and the DRAM stops working.

I tried to reduce the lenght of all the nets, the longest has 29mm. On the other hand I didn't take into account the recommendations about the power plane and the same number of vias on each data net.

I think I should to improve on the following:

1. Make a good 2.5V power plane (I already have a via and a capacitor by pin).

2. Reduce the number of vias and use the same number in all the data nets.

3. Reduce the lenght of all the nets and match by groups (data and adress).

Do you think that would be useful to place termination resistors or <30mm is an acceptable lenght to avoid reflections? (the guidelines recommend <22.5mm).

Any other advice?

Thanks a lot.

Manu

[DaviddeBethel]

Hi Dan,

Thanks for the quick reply!  

Phew! I had a panic there for a moment.  I didn't think it would be that critical at the speeds we are talking here but you never know.  I thought I was going to have to reroute for new track widths to meet impedance criteria.

I vaguely remember some of the microstrip design principles from Uni and wa not looking forward to delving back into it again!  Although, the day when I have to may be fast approaching.

Many thanks for your comments, i have a bit more confidence in the design now!

Just out of interest did you end up weaving your tracks around to match lengths! I f so should I be aware of any pitfalls in this area?

David

[danix]

David,

In my design I only matched the length of the data groups. I didn worry about the address signals that much. I used a 4-layer board with the BGA package; I've compromised the routing guidlines a lot, but it turns out that my board is performing quite well just as the EVK.

I don't think you've to worry about impedance, make sure you've kept the following four and you're safe to go:

1. A solid uninterrupted ground plane below the SDRAM traces.

2. Do not populate any noisy component near the SDRAM, like switching regulator, RF transceivers,...

3. Put sufficient decoupling capacitors as close as possible to all DDR power pins.

4. match all DDR signal groups and keep the traces as short as possible, especially the data groups.

Good luck,

--Dan

[DaviddeBethel]

Hi guys,

Just found this thread whilst looking for info on the web about routing SDRAM.  I am using some Micron SDRAM @133Mhz, not DDR with an IMX257 and I have a question!

How critical is the 50ohm impedance?  All my lengths are matched to 0.03mm but I have taken into consideration the charactersitic impedance!!! Is this going to be a problem?

Many Thanks

deBoogle

[FelixVidal]

If you would be more or less confident to have an acceptable routing and, if you'll have money, you should use a postlayout PCB simulator. Otherwise you are sowing dragon's teeth.

[kamejoko80]

With FBGA package we must use at least 6 layers PCB, so I think It is not much more complex than 2 layers PCB designing, be cause we have more space to route, easy to control the line impedance...

Firstly for DDR signals we should keep Impedance about 50 ohm, and trace length matching.

Reference the following link for setting up the PCB stack up and etc...

http://beagleboard.org/hardware/design

[danix]

Thanks Minh, you are using the LQFP mine is the FBGA package. routing is much easier with the LQFP, but it misses the features I want to use, like SPDIF, LCD 24bpp dotclk mode, and onchip amplifier

[kamejoko80]

Hi,

Don't worry about that. My longest trace is 40mm (ADDR signal). Try to keep the length of the data group shortest as possible.

[danix]

Thanks Ahmet, That was exactly the kind of information I was looking for;

[AhmetYUCE]

Take a look at AN4215 "i.MX28 Layout and Design Guidelines". Although iMX23 supports DDR1 and iMX28 uses DDR2, information in AN4215 could be useful for DDR1 too. It contains information about acceptable DDR2's trace length mismatches.