i.MX23 DC-DC clock domain

[lategoodbye]

Hi,

according to this question https://community.freescale.com/thread/352940 i created a little ASCII art of the i.MX23 DC-DC clock domain accordingly to the diagramm in the RM:

https://gist.github.com/lategoodbye/e1f462869bfd94843d20

I guess the third parent clock is clk_tv108m_ng because the frequencies for values 0x04, 0x05, 0x06 and 0x07 doesn't fit to ref_pll or ref_xtal.

Is it correct?

Thanks Stefan

[igorpadykov]

Hi Stefan

i.MX28 has not clk_tv108m_ng, but the same FREQSEL settings,

so seems this clock produced just from separate PLL PFD.

Best regards

igor

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[lategoodbye]

Hi igor,

i noticed in i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 there are the same values for FREQSEL as in the i.MX23 Reference Manual.

But in i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 they are a little bit different.

What is the right version?

Thanks

Stefan

[igorpadykov · Accepted solution]

Hi Stefan

right is latest revision

Best regards

igor