i.MX ULL powerdown squence

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i.MX ULL powerdown squence

Contributor III


When I checked the PF1510, I was able to set 2ms in the power down sequence.

Is there a way to keep the VDD_HIGH_IN and VDD_HIGH_IN power down sequences for more than 2ms in the event of a sudden voltage drop?

If I can't keep the sequence, do I need to change the CPU? i.M6UL → i.MX6ULL

I tried to match the order with the capacitor, but it may change depending on the current value. Is it possible to adjust the order with just the capacitors?

Why follow the VDD_HIGH_IN and VDD_HIGH_IN powerdown sequences? Is it because the processing of software on the CPU is affected? Will the backflow shorten the life of the hardware?

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NXP TechSupport
NXP TechSupport

Only 2ms delay is supported with PF1510.

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