i.MX RT685 Phase Align CLKOUT and CTIMER

[mzielinski]

Hello,

Is it possible to deterministically phase align the output of a CLKOUT pin and a CTIMER? I have a requirement to create a periodic burst of 16 clock cycles at 48.96MHz, with a burst rate of 1.44MHz. At the moment I do the following: I' configure audio_pll_clk to be 391.68MHz, and I set CLKOUTDIV to 8. I also select audio_pll_clk as the CTIMER3 clock. Then I configure a PWM output in CTIMER3 with frequency 1.44MHz (match value of exactly 272 @ 391.68MHz) and a duty cycle equivalent to 16 clock periods of 48.96MHz. The 48.96MHz CLKOUT is connected to the input of a tri-state clock buffer IC, and the PWM output of the CTIMER is connected to the OE (output enable) of the clock buffer. The output is then the periodic burst of 16 clock cycles that I need, with one small problem.

The problem I have is the CTIMER PWM output is enabled with an random phase offset relative to the 48.96MHz CLKOUT, which results in the clock buffer being enabled and disabled at the wrong time, sometimes cutting off the clock pulses. 

Is there any way to start the CTIMER PWM output at a known phase relative to CLKOUT?

Please let me know if more info is required.

Thanks.

-Mike

[xiangjun_rong]

Hi, Michal,

Regarding your question, I suppose that if the CTimer uses CLKOUT pin clock as tick to generate PWM signal to gate the buffer, you can solve the no-alignment problem.

But the CLKOUT signal is not the clock source of CTimer, in the case, you can connect the CLKOUT pin to a capture pin with external cable, and configure the CTimer so that the CTimer can count the clock signal from capture pin. Pls refer to Table 419, you can set the CTMODE as 0x01, and set the CINSEL bit based the capture pin you selected.

The screenshot is from UM11147.pdf

Hope it can help you

BR

XiangJun Rong

[mzielinski]

Hi XiangJun,

Thanks for your quick reply. Using CLKOUT as the clock source of the CTIMER is a good idea, but I am not sure if it will work for me. I believe that I need high resolution for creating the gate signal, that's why the I have the CTIMER running at 8 times the frequency of the CLKOUT, so that I can adjust the rising and falling edges of the gate signal by steps of 1/8 of a clock cycle of CLKOUT to calibrate for routing delays on my board, etc. Maybe it's not actually necessary, I will reconsider it.

Taking another look at the datasheet, maybe there is also another way: from page 430 of the datasheet, setting the correct bits in CTCR can clear the timer and prescaler of the CTIMER on a rising or falling edge of a capture input. I seems to me like resetting the count on a CLKOUT rising edge would create the deterministic relationship between CLKOUT edges and the CTIMER counter value that I'm looking for, even with the CTIMER running at 8x the speed of the CLKOUT. Do you agree?

-Mike

[xiangjun_rong]

Hi, Mike,

I agree with you, I think your solution is okay.

I drew a diagram as the following, if you use capture signal to reset CTimer32, it appears you have to use 1.44Mhz signal, pls determine yourself.

BR

XiangJun Rong

[mzielinski]

Hi XiangJun,

Just wanted to report that I implemented my idea and it works exactly like I need it to.

Your diagram matches my setup, except that there is no /34 block between the CLKOUT and CTIMER capture input. I am resetting the CTIMER using the 48.96MHz CLKOUT directly. The CTIMER, by counting 272 cycles of the 391.68MHz clock, is what creates the 1.44MHz PWM that I use.

Best,

-Mike