i.MX CAAM DMA restrictions

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i.MX CAAM DMA restrictions

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vsiles
Senior Contributor I

Hi !

I'm currently developing a bare metal driver for the CAAM of a i.MX6 board.

For the documentation I see that input/output ring addresses must be 4-byte aligned.

However with this restriction only, I sometime fail to start the RNG component, and the only way to fix things is to have a bigger alignment constraint on these addresses.

In Linux and U-boot, I can see they always allocate buffer with at least 64 byte alignment (even 4k in linux iirc), so I'm wondering if the 4-byte constraint from the documentation is correct or if I need to allocate my buffer with a more restrictive address.

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vsiles
Senior Contributor I

Thanks for the idea, it pointed me to the right direction even if it wasn't exactly the problem: my cache invalidation routine triggered some 'clean' cache operations because the DMA buffer span over a cache line boundary, erasing the content written by the DMA in the first place.

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Vincent

this may be caused by burst size value, which could be 32 bytes or 64 bytes, as indicated by

the BURST field of the Master Configuration Register (MCFGR) and described in sect.5.5.1.1

DMA interface(AXI master bus) i.MX6 Security Reference Manual available on link

Q&A: How is mx6 PMIC_ON_REQ under SW control? 

Best regards
igor
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94 Views
vsiles
Senior Contributor I

Thanks for the idea, it pointed me to the right direction even if it wasn't exactly the problem: my cache invalidation routine triggered some 'clean' cache operations because the DMA buffer span over a cache line boundary, erasing the content written by the DMA in the first place.

View solution in original post

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