Hello.
I have a question about i.MX93 LPDDR4 routing design.
Are the values listed in “Table 16. i.MX 93 LPDDR4/4X-3733 routing recommendations” in the i.MX93 Hardware Guide the delay values calculated when designing Allegro?
The delay time is considered as part of the routing design, but the simulation results show a slight discrepancy because the delay time is not determined by the routing length alone.
2.CK_T/CK_C is listed as Max 200ps, but in “Table 17. LPDDR4/4X delay matching example (CA/CTL signals)”, “Total Net Delay = (PCB + Pkg) Delay” exceeds 200ps.
(Are these values also Allegro design values or values from simulation results?)
3. The following is described in the “Considerations” section.
Match CA5, CA4, CA3, CA2 within 2 ps
Match CA1, CA0, CKE1, CKE0 within 2 ps
Why do the delay times have to be matched within a group?
I don't see the need to match the delay time so strictly, since I think that as long as the delay is kept to the clock standard as a signal, there is no problem in operation.
I think it is better to align the minimum necessary wiring length (delay time) within the operating range, because adjusting the wiring length more than necessary will adversely affect signal quality and crosstalk effects.
