i.MX 8X L2 cache direct access

[EAlepins]

Hi,

I would like to know if it is possible to inspect the contents of the i.MX 8X (QXP) Cortex-A35 cluster’s L2 cache. The idea is to see what lines are allocated, which are dirty, etc. The objective is to understand how the L2 cache is exercised by our software and also to validate that test software effectively puts L2 cache in the desired state (e.g. 100% dirty, etc.) A JTAG-only access would also be fine.

Thanks,

Étienne

[Zhiming_Liu · Accepted solution]

Hi

 Expert team reply:there is no method for L2 cache direct access

BR

Zhiming

[Zhiming_Liu]

Hi

As  my experience, perf tool in linux can analyse cache hit.

But in my previous test, perf tool on our yocto image only support L1 cache hit,

root@imx8qxpmek:~# perf list

List of pre-defined events (to be used in -e):

branch-instructions OR branches [Hardware event]
branch-misses [Hardware event]
bus-cycles [Hardware event]
cache-misses [Hardware event]
cache-references [Hardware event]
cpu-cycles OR cycles [Hardware event]
instructions [Hardware event]

alignment-faults [Software event]
bpf-output [Software event]
context-switches OR cs [Software event]
cpu-clock [Software event]
cpu-migrations OR migrations [Software event]
dummy [Software event]
emulation-faults [Software event]
major-faults [Software event]
minor-faults [Software event]
page-faults OR faults [Software event]
task-clock [Software event]

L1-dcache-load-misses [Hardware cache event]
L1-dcache-loads [Hardware cache event]
L1-dcache-store-misses [Hardware cache event]
L1-dcache-stores [Hardware cache event]
L1-icache-load-misses [Hardware cache event]
L1-icache-loads [Hardware cache event]
branch-load-misses [Hardware cache event]
branch-loads [Hardware cache event]
dTLB-load-misses [Hardware cache event]
iTLB-load-misses [Hardware cache event]

About L2 cache, I will update if i get expert team reply.

BR

Zhiming