i.MX 8QM with 2x 4GiB (=8GiB) LPDDR4 => kernel crash

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i.MX 8QM with 2x 4GiB (=8GiB) LPDDR4 => kernel crash

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Stefan_ng
Contributor II

Dear All,

I'm having a problem with a customized i.MX 8QM board with 8GiB (2x 4GiB) LPDDR4 memory.
The same PCB with physical equipped 2x 2GiB is running well.

I used the RPA for 8GiB, tested this configuration with NXP DDR Stress Test sucessfully and used this configuration to build my "own" SCFW.
Then I configured my board header file to support the 8GiB:
#define CONFIG_SYS_SDRAM_BASE    0x080000000
#define CONFIG_NR_DRAM_BANKS    2
#define PHYS_SDRAM_1                      0x080000000
#define PHYS_SDRAM_2                      0x880000000
#define PHYS_SDRAM_1_SIZE                 0x080000000      /* 2 GiB */
#define PHYS_SDRAM_2_SIZE                 0x180000000      /* 6 GiB */

The U-Boot and Kernel (4.14.98) are booting.
But, when I start a "dd if=/dev/mmcblk0 of=/dev/null", the system crashes after ca. 1.7GiB. (mmcblk0 is a eMMC with e.g. 15.3GiB; system is booting from uSD)
When I start "dd if=/dev/sda1 of=/dev/null" (sda1 is 4GB USB flash drive), the system crashes after ca. 950MiB.

I reconfigured the PHYS_SDRAM_2_SIZE to 0x08000000 (2 GiB). For this I don't encountering such problems (no hardware change, no change in SCFW, too!).

Does someone has similar problems? Or does anyone have a working 8GiB (or even higher) memory configuration?
Which configuration did I missed?

Here is my "log", when the failure occured:
root@imx8qm:~# dd if=/dev/mmcblk0 of=/dev/null status=progress
1775244800 bytes (1.8 GB, 1.7 GiB) copied, 12 s, 148 MB/s[  431.735398] arm-smmu 51400000.iommu: Unhandled context fault: fsr=0x402, iova=0xfc55b000, fsynr=0x100013, cb=1
[  431.745513] mmc0: running CQE recovery
[  431.763388] arm-smmu 51400000.iommu: Unhandled context fault: fsr=0x402, iova=0xfc55b000, fsynr=0x100013, cb=1
[  431.773452] mmc0: running CQE recovery
[  431.790401] ------------[ cut here ]------------
[  431.795042] WARNING: CPU: 0 PID: 109 at /usr/src/kernel/drivers/iommu/io-pgtable-arm.c:577 __arm_lpae_unmap+0x448/0x4c0
[  431.805830] Modules linked in: crc32_ce crct10dif_ce galcore(O) fuse g_serial
[  431.813004] CPU: 0 PID: 109 Comm: kworker/0:1 Tainted: G        W  O    4.14.98-dev #1
[  431.820927] Hardware name: xxx iMX8QM xx (DT)
[  431.826258] Workqueue: events mmc_mq_recovery_handler
[  431.831318] task: ffff800975218d80 task.stack: ffff00000a790000
[  431.837243] PC is at __arm_lpae_unmap+0x448/0x4c0
[  431.841951] LR is at __arm_lpae_unmap+0x2d8/0x4c0
[  431.846661] pc : [<ffff000008656650>] lr : [<ffff0000086564e0>] pstate: 80000145
[  431.854058] sp : ffff00000a7938e0
[  431.857377] x29: ffff00000a7938e0 x28: 0000000000000000
[  431.862694] x27: 0000000000000000 x26: 0000000000000001
[  431.868019] x25: 0000000000000009 x24: 0000000000000001
[  431.873345] x23: 0000000000001000 x22: ffff800970051d48
[  431.878670] x21: 0000000000001000 x20: 0000000000000003
[  431.883996] x19: ffff800970051e00 x18: 0000000000000010
[  431.889321] x17: 0000ffffa743ac18 x16: 0000000000000000
[  431.894647] x15: ffffffffffffffff x14: 0000000000000000
[  431.899972] x13: 0000000000000000 x12: 000000644570e4dd
[  431.905297] x11: 0000000000000001 x10: 0000000000000003
[  431.910614] x9 : 0000000000000004 x8 : 000000000000000c
[  431.915931] x7 : 0000000000000009 x6 : ffff800078114900
[  431.921248] x5 : 0000000000000120 x4 : ffff800078114000
[  431.926573] x3 : 0000000000000003 x2 : 0000000000001000
[  431.931890] x1 : 00000000fc520000 x0 : ffff800970051e00
[  431.937209] Call trace:
[  431.939664] Exception stack(0xffff00000a7937a0 to 0xffff00000a7938e0)
[  431.946121] 37a0: ffff800970051e00 00000000fc520000 0000000000001000 0000000000000003
[  431.953961] 37c0: ffff800078114000 0000000000000120 ffff800078114900 0000000000000009
[  431.961796] 37e0: 000000000000000c 0000000000000004 0000000000000003 0000000000000001
[  431.969635] 3800: 000000644570e4dd 0000000000000000 0000000000000000 ffffffffffffffff
[  431.977469] 3820: 0000000000000000 0000ffffa743ac18 0000000000000010 ffff800970051e00
[  431.985307] 3840: 0000000000000003 0000000000001000 ffff800970051d48 0000000000001000
[  431.993141] 3860: 0000000000000001 0000000000000009 0000000000000001 0000000000000000
[  432.000977] 3880: 0000000000000000 ffff00000a7938e0 ffff0000086564e0 ffff00000a7938e0
[  432.008814] 38a0: ffff000008656650 0000000080000145 ffff00000a793930 ffff000008e1a0d8
[  432.016650] 38c0: ffffffffffffffff ffff00008977d647 ffff00000a7938e0 ffff000008656650
[  432.024488] [<ffff000008656650>] __arm_lpae_unmap+0x448/0x4c0
[  432.030236] [<ffff0000086564e0>] __arm_lpae_unmap+0x2d8/0x4c0
[  432.035987] [<ffff0000086564e0>] __arm_lpae_unmap+0x2d8/0x4c0
[  432.041738] [<ffff0000086564e0>] __arm_lpae_unmap+0x2d8/0x4c0
[  432.047489] [<ffff00000865670c>] arm_lpae_unmap+0x44/0xa0
[  432.052899] [<ffff000008658de8>] arm_smmu_unmap+0x18/0x30
[  432.058313] [<ffff000008652b2c>] __iommu_unmap+0xdc/0x1b0
[  432.063722] [<ffff000008652c10>] iommu_unmap+0x10/0x18
[  432.068871] [<ffff00000865455c>] __iommu_dma_unmap+0x44/0x98
[  432.074533] [<ffff0000086554c8>] iommu_dma_unmap_sg+0x88/0xa8
[  432.080292] [<ffff00000809ab60>] __iommu_unmap_sg_attrs+0x78/0x88
[  432.086397] [<ffff000008ae0820>] cqhci_post_req+0x50/0x70
[  432.091809] [<ffff000008aa7640>] mmc_cqe_post_req+0x18/0x28
[  432.097395] [<ffff000008ab7ce8>] mmc_blk_cqe_complete_rq+0x30/0x140
[  432.103673] [<ffff000008ab84fc>] mmc_blk_cqe_req_done+0x34/0x40
[  432.109599] [<ffff000008aa75f4>] mmc_cqe_request_done+0x3c/0x70
[  432.115535] [<ffff000008ae28c4>] cqhci_recovery_finish+0x114/0x270
[  432.121727] [<ffff000008aa8e34>] mmc_cqe_recovery+0xe4/0x100
[  432.127392] [<ffff000008abc0d0>] mmc_blk_cqe_recovery+0x20/0x68
[  432.133326] [<ffff000008abcae8>] mmc_mq_recovery_handler+0x40/0x88
[  432.139524] [<ffff0000080e76ec>] process_one_work+0x1d4/0x348
[  432.145276] [<ffff0000080e78a8>] worker_thread+0x48/0x470
[  432.150686] [<ffff0000080edbac>] kthread+0x12c/0x130
[  432.155664] [<ffff000008084ed8>] ret_from_fork+0x10/0x18
[  432.160985] ---[ end trace 8a0faccfe6294236 ]---
[  432.165739] ------------[ cut here ]------------


Thank you!
Stefan

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1 Solution
977 Views
Stefan_ng
Contributor II

Solution: within board header file, setting CONFIG_NR_DRAM_BANKS to '4'

View solution in original post

3 Replies
977 Views
gusarambula
NXP TechSupport
NXP TechSupport

Thank you, Stefan! For sharing the solution to this issue! I'm sure it will help other Community users.

Regards,

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Stefan_ng
Contributor II

Solution: within board header file, setting CONFIG_NR_DRAM_BANKS to '4'

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Velvettiere
Contributor I

Hi all. Thank you very much for your contribute in this post.

We have a very similar problem in our custom board with IMX8QM. The LPDDR4 design match the NXP specification that are in the “IMX8HWDG Rev 2.4p 062021.pdf.” No issue on power and signal integrity simulation (Keysight ADS tool has been used for these). We have Micron 2x4GiB MT53E series LPDDR4 memory at 3200MT/s (1600MHz DDR clock requency).

We don’t reach to find out the “CONFIG_NR_DRAM_BANKS” define for try to chage it as reccomended by you.

We use this SW configuration:

SCU at rev 1.11.1

M4+Linux: Linux 5.10.72_2.2.0 digital cockpit

RPA23 file has changed to set the MT53E at 2x4GiB and the best ODT termination for our PCB find out the simulation of signal integrity.

Can you help us in this challange for find and try to change this define?

Thank you very much. Bye.

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