i.MX 8M Plus: Sharing external DDR between M7 and A53 cores

[df123]

Hi,

We're investigating the possibility of using the external DDR for both the M7 (FreeRTOS) and A53 (Linux) application (separate partitions) for both code & data. What are the implications on performance of this setup? We're mainly interested in the real-time performance of the M7 core during concurrent access to the external memory from the A53 cores. What are the latencies to be expected?

How does the DDR controller / AXI bus prioritize reads/writes from the M7 core with respect to other bus participants? Is there a way to adjust it for our use case?

[BiyongSUN]

BSP release linux and m-core sdk, already has the example. 

Do you have the code in hand?

1. you need to make a "hole" on DDR of a-core linux side, linux could not see it and m-core use that ddr region in that "hole".

imx8mp-evk-rpmsg.dts is example  a-core linux side to make a "hole" and m-core sdk example rpmsg tty and rpmg pingpong is the example how to use the "hole".   

If you need m-core code also running in ddr, you need to change about example settings and use ddr link script for m-core sdk.

2. If the shared ddr(the hole) is not in the non-cache region, you need to change the m-core MPU. details,   please download the related document from arm web site. 

The following link explains the about points. 

Although, it is old i.MX6SX(A9 +  M4), but technically it is same for A53 +  M7. 

08/10/2018:

i.MX6SX M4 MPU Settings For RPMSG update

i.MX6SX_M4_MPU_Settings_For_RPMSG_08102018.pdf

[jamesbone]

Here is an example on how to share memory in DDR between M4 and Cortex A53 cores.

/*
       Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4
       cores.
       You can put global or static uninitialized variables in NonCacheable section(initialized variables in
       NonCacheable.init section)
       to make them uncacheable. Since the base address of MPU region should be multiples of region size, to make it
       simple,
       the MPU region 1 set the address space 0x80000000 ~ 0xFFFFFFFF to be non-cacheable(disable sub-region 6,7 to use
       the background memory
       attributes for address space 0xE0000000 ~ 0xFFFFFFFF). Then MPU region 2 set the text and data section to be
       cacheable if the program running
       on DDR. The cacheable area base address should be multiples of its size in linker file, they can be modified per
       your needs.
    */

    /* Select Region 1 and set its base address to the DDR start address. */
    MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);

    /* Region 1 setting:
     * 1) Enable Instruction Access;
     * 2) AP = 011b, full access;
     * 3) Shared Device;
     * 4) Sub-Region 6,7 Disabled;
     * 5) MPU Protection Region size = 2048M byte;
     * 6) Enable Region 1.
     */
    MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (0xC0 << MPU_RASR_SRD_Pos) |
                (30 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;