Dear NXP team,
we're working on a QNX driver for the i.MX 8M Plus (industrial grade, i.e. with the CAN FD controller) FlexCAN in CAN FD mode.
Our main problem is that we'd like to configure the FlexCAN module for high CAN FD bitrates. The FlexCAN chapter talks about up to 8 Mbit/s, but that is depending on several restrictions. The one that I'm most concerned about right now is this: "The peripheral clock frequency cannot be smaller than the oscillator clock frequency".
The "functional" clock for the CAN module seems to be CAN1/2_CLK_ROOT (called "CAN1_PECLK_MUXED" in another table...), which the RM says can be up to 80 MHz, but that would mean that we have to increase the IPG_CLK_ROOT to > 80 MHz.
The RM uses several names for the clocks that I find rather confusing.
- The "Table 5-2. System Clocks" lists a whole bunch of clocks:
- can1/2.ipg_clk, ipg_clk_chi, ipg_clk_pe, ipg_clk_pe_nogate, ipg_clk_s, ipt_clk, osc_clk
- can1/2_mem.can_hclk
- The FlexCAN chapter on clocks (11.8.2.10 Clocks) describes only a subset of these:
- ipg_clk, ipg_clk_chi, ipg_clk_pe, ipg_clk_pe_nogate and ipg_clk_s
- there's no mention of ipt_clk, osc_clk and can1/2_mem.can_hclk
- There's a whole bunch of restrictions described in chapter 11.8.2.10.1 "Clock domains and restrictions", but that chapter mostly talks about "peripheral clock" and "oscillator clock" without referencing the clocks mentioned before.
- I believe that
- "peripheral clock" is the same as "bus domain feeds the Control Host Interface (CHI) submodule" and that is ipg_clk_chi, which is driven by IPG_CLK_ROOT
- and "oscillator domain feeds the CAN Protocol Engine (PE) submodule" is the ipg_clk_pe, and that is the "oscillator clock".
- Is that correct?
- What are the other clocks (ipt_clk, osc_clk and can1/2_mem.can_hclk) used for in the FlexCAN module?
- ipg_clk_chi is driven by IPG_CLK_ROOT. According to the RM this clock could be up to 133 MHz, but both on the SoM we're working with and on the i.MX 8M Plus EVK the IPG_CLK_ROOT is running at 66 MHz. That clock also seems to be used by a large number of peripherals, so I don't want to mess with this clock without knowing what I'm doing. It seems pretty global, used as the "ipg_clk" for a lot of different modules, but the RM appears to use "ipg_clk" in different contexts with different meaning, and different limitations.
- E.g. there's a SPBA module with a spba1.ipg_clk that is driven by IPG_CLK_ROOT, but that SPBA module is described as being limited to 67 MHz operation, suggesting we would run into problems if we increased IPG_CLK_ROOT to 133 MHz.
- What "is" this ipg_clk in general, and can we safely increase IPG_CLK_ROOT to 133 MHz?
Best Regards,
Dominic
