For DDR4 operation at 3200 MT/s on i.MX 8M Plus,
could you please clarify the recommended design approach
for PCB routing and length matching?
Specifically:
- Is DDR4-3200 operation assumed and validated by design
(with appropriate board design)?
- In the absence of a DDR4 reference board,
what should be considered the primary guideline
for length matching and skew control?
A: We only supply the hardware guide for the i.MX8MP, for the hardware design using the DDR4 please refer to it. And for the i.MX8MP using the DDR4, we have the validation board design, I will share it to you.
Can AN5097 be used as a general DDR4 routing guideline
for i.MX 8M Plus designs, even though it is not
device-specific, provided that standard DDR4
signal integrity rules are followed?
A:No, do not refer to it, for the i.MX8MP please following the hardware guide for it special.