i.MX 8M Nano DDR Tool

[NATHANKLOGIC]

I am working with a custom designed board that utilizes either the i.MX 8M Mini or i.MX 8M Nano processor with LPDDR4 (x32 or x16 per processor support).  Our last build of boards included I-Temp rated processor and RAM chip.  When testing the i.MX 8M Mini Quad option, the DDR Tool stress test from NXP operated fine from -40C to +85C as expected (once I set the "LPDDR4 MR4 manual de-rate workaround - Temperature Derating Options for errata e50125" to Option 1 in the MX8M_Mini_LPDDR4_RPA_v15.xlsx spreadsheet).

However, when I tried to test the i.MX 8M Nano I was seeing consistent memory failures when getting near 0C and below.  I noticed that the preliminary_MX8M_Nano_LPDDR4_RPA_v1.xlsx spreadsheet did not have the same option for temperature derating, but I went through the registers and changed them the same way they were changed for the Mini (taking into account the different RAM clock speed).  Changing these values did make the +85C testing pass, but it had no effect when testing at 0C and below.  I made the refresh rate 4x and added all the derating values from the RAM datasheet into the timing, but it still had no effect on the negative temperature testing.  I had 3 boards that would start to fail at +5C (ambient) or slightly below.  They all would fail (only at cold temperatures) during the first part of the RAM stress test when the test is run at the fastest speed; example output:

t0.1: data is addr test
...Address of failure: 0x0000000060000000
Data read was: 0x00FF03FF00FF03FF
But pattern was: 0x0000000040000000

The failures were always at this address and pattern, but the data read was not always the same.

I took the same RAM timings and fed them into our version of the NXP Linux BSP (modified only to support our board) and ran the boards through a script that would copy a 1GB file from a USB drive to the onboard eMMC, copy a 31MB file from USB to both the onboard uSD card and the onboard QSPI; it would then do an MD5SUM of all the copied files to verify the copies were successful.  It continually loops on this, deleting the files in between cycles.  I was able to successfully run this through 10 temperature cycles from -40C to +85C with a 60 minute soak.  So I believe our Nano hardware is OK on the LPDDR4 interface (our Mini hardware passes this same testing).

Has there been other reports of the i.MX 8M Nano LPDDR4 DDR Tool stress testing failing over I-Temp?  Any ideas what might make that tool fail at 0C and below?

[nxf63675]

Hi nathank‌,

Also could you try setting this parameters please and see this help you to pass the test.

Fine tune DDRPHY paramters as follows
ddrparam set ODTImpedance xx
ddrparam set TxImpedance xx

Regards,

Israel H.

[nxf63675]

Hi nathank‌,

Could you share with us the DDR part from the schematics, the LPDDR4 part that you are using and the spreadsheet with the configuration/modification please.

We will review this and come back with you.

Regards,

Israel H.

[NATHANKLOGIC]

Attached is the RAM page from our schematics.  These are the same schematics for both Mini and Nano for our SOM.  The RAM part we used is a Micron MT53D512M16D1DS-046 IT; it is a 1GB x16 chip rated for I-Temp.

Also attached are 2 timing spreadsheets that I used.  The "_itemp_derate" replicates what was done for the Mini LPDDR4 timing spreadsheet by picking "Option 1" of the "LPDDR4 MR4 manual de-rate workaround".  The "_itemp_derate_with_all_derating" spreadsheet includes additional derating from the Micron datasheet for extreme temperature operation; I added the offsets in the formulas of the spreadsheet based on the max values provided by Micron.  Neither of these 2 spreadsheets produced timings that worked at negative temperatures using the NXP DDR tool, however the "itemp_derate" timings worked from -40C to +85C using our Linux BSP while running MD5SUMs (I did not try the "_with_all_derating" in Linux since the less severe timings worked).  Note: these 2 spreadsheets update the full speed timing (1600MHz), but the 200MHz and 50MHz timings do not update automatically in all places; I might of added that to these spreadsheets (I cannot remember), but if not I manually changed those values in the configuration file by doing a compare to our Mini DDR timings.  The full speed testing is what failed, anyway, not the 200MHz or 50MHz.

I did not try modifying the OTD or tximpedance parameters, yet, but that is on my list to try to reduce power consumption on the bus.  The values in the spreadsheet for the Nano are the same values we used on the Mini processor which worked over all temperature ranges (same PCB, only difference was a x32 Mircon part and the Mini processor).

Thanks for looking into this.

[maheshmuni]

Hi NATHANKLOGIC

Can you tell me how do you generated the lpddr4_timing.c file for the lpddr MT53D512M16D1DS specific (if possible please share the file lpddr4_timing.c for the above micron model)?

I have tried with MX8M_Nano_LPDDR4_RPA_v7.xlsx, by editing the 'Register Configuration' tab and able to get the tab 'DDR Stress test'  updated. But there is no information how to map these values to lpddr4_timing.c file.

Thanks

Mahesh Muni