i.MX 8M Mini CSI camera clock lane

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i.MX 8M Mini CSI camera clock lane

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Contributor I

I am running into a problem here: The MIPI clock from a camera sensor is sometimes not detected: Register MIPI_CSI_DPHY_STATUS transitions from Bitfield STOPSTATEDAT 1 to 0 (which is good) but Bitfield STOPSTATECLK remains at 1, which means: "Clock lane is in Stop State".

MIPI_CSIS_DPHYCTRL should be set correctly.

Q1: Any ideas what to check?

In the TRM I cannot find any specific information about specific requirements regarding the clock.

Q2: TRM of i.MX 8M Mini Register MIPI_CSI_CSIS_CLOCK_CTRL:0x32e30008 does not describe Bit 0 at all, but TRM of i.mx7 does as WCLK_SRC. Why is that?

Q3: TRM lacks description of WCLK_SRC while referencing WCLK_SRC in some places like MIPI_CSI_INTERRUPT_SOURCE_0 Bit ERR_OVER. Is this a Bug?

Q4: On i.MX 8M Mini the driver sets in Register MIPI_CSI_CSIS_CLOCK_CTRL:0x32e30008 Bit Number 0 (WCLK_SRC) to value 1, but reading value of Bit Number 0 back it is a 0. Why is that? Shouldn't it be 1?

Q5: Is MIPI PHY (described in TRM i.MX 8M Mini 13.6.10 MIPI PHY Memory Map/Register Definition) somehow related/connected to the CSI (camera interface)?

Q6: If yes: In TRM i.MX 8M Mini "13.6.10 MIPI PHY Memory Map/Register Definition" I cannot find any absolute register-Address like I do for e.g. MIPI_CSI_DPHY_STATUS = 0x32e30020. What is the absolute register address for the MIPI PHY?

 

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NXP TechSupport
NXP TechSupport

Q1: Any ideas what to check?

>you can check if you can get the correct mipi clock or not, like PHY reference clock and clk_ui

Q2,Q3, Q4:

>I got information:"

"checked with IP team that we don't have "WCLK_SRC" bit any more.

The original purpose of "WCLK_SRC" is to set clock speed, but it has been removed after fixed it as max speed case internally.we removed "WCLK_SRC" related description from ERR_OVER "

Q5:

>yes

Q6:

> I don't know what you mean, if you mean Absolute register address, pls refer to the 13.4.15 MIPI CSI Memory Map/Register Definition of Reference Manual

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