i.MX 8M DDR4 Dual Rank wiring [CK_t+c_A+B vs. CKE_0+1]

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i.MX 8M DDR4 Dual Rank wiring [CK_t+c_A+B vs. CKE_0+1]

Contributor II

Trying to complete schematics of a minimum i.MX 8M Mini/Nano design together with an Xilinx Artix7. Unfortunately, I have never worked with DDRx memories before, though I know my way around High-Speed PCB design. 

So far I have been stitching together HW information from data sheets, reference manuals, HW Design Guides and - more importantly - any and all available schematics of i.MX8 development boards. This PCB of ours is supposed to support both i.MX 8M Mini and Nano.

We choose to stay as close to the reference design as possible, to maximise our chances that the provided support software [uBoot/Linux] just works out-of-the-box. The idea is to use four of the very same MT40A512M16LY x16 DDR4 devices, but in two Ranks of x32 bit each. On opposite sides of the PCB with mirroring enabled. And this is where I get confused. 

AN5097 - Hardware and Layout Design Considerations for DDR4 SDRAM Memory Interfaces:

#33 :: Ensure one clock pair is used for each rank of memory in fly-by topology following the address/command bus routing.

This I interpretate the following way:

=> route clock CK_t+c_A to Rank[0], point-to-point-two-chips-flyby

=> Route clock CK_t+c_B to Rank[1], point-to-point-two-chips-flyby

=> Route CS0_n to Rank[0], point-to-point-two-chips-flyby

=> Route CS1_n to Rank[1], point-to-point-two-chips-flyby

Now, in spite of the apparent confusion convolving channels [A/B] and ranks [0/1] naming conventions for DDR4, I assume:

• CKE0 applies to CK_t+c_A and hence should be routed to Rank[0], point-to-point-two-chips-flyby?

• CKE1 applies to CK_t+c_B and hence should be routed to Rank[1], point-to-point-two-chips-flyby?

Also, I am somewhat wary of the Chip ID (Cx) die selects for 3D-stacked DDR4 SDRAM devices. There are just two of them on the i.MX 8M Mini/Nano, but these are labelled C0 (DRAM_AC03) and C2 (DRAM_AC32,) with C1 missing.

My guess is that either there is a missing C1 label on DRAM_AC22, in «Table 20: DDR3L/LPDDR4/DDR4 connectivity» of the «i.MX 8M Mini Hardware Developer’s Guide» or else the C2 label should in reality read C1.

( According to JEDEC JESD79-4B, the CS1_n in use with Dual-Die Packages takes on the role of C1 in the case of 3D Stacked Die Packages on the SDRAM side of things. Is this the case for the i.MX 8M CPU side as well? This would then obviously cost me the second Rank, if ever in exchange for 3D Stacked Dies. ) 

i.MX 8M Mini - DDR Addr+Ctrl.png

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NXP Employee
NXP Employee



  I've sent You directly some comments.



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