Hi Igor,
Thanks for helping. Unfortunately, creating a service request is not an option for me at the moment . Moreover, beyond than just getting some results I wanted to tell how to optimize the MX6UL performance in a bare-metal environment to compare it to a Linux environment. From this post I think it can be that I still need to activate L1 and L2 cache of the processor.
Could you point me out how to enable both cache in the initialization for this processor in a bare-metal enviroment? I'm using the IAR ARM 8.32 compiler for this test.
Regarding the source code optimization for the CoreMark benchmark: I would actually want to avoid that the benchmark can be optimized, either by modifying it by hand or letting the compiler optimize it. As I'll be using 2 different compilers to run my tests (probably GCC and ARM) I wouldn't like to measure how well those 2 compilers can optimize the code but what is the overhead of one target environment over the other running on the same processor + RAM. I found this in the CoreMark site:
"Unlike Dhrystone, CoreMark has specific run and reporting rules, and was designed to avoid problematic aspects of Dhrystone. For example, major portions of Dhrystone actually expose the compiler’s ability to optimize the workload rather than the capabilities of an MCU or CPU. Dhrystone is thus more revealing as a compiler benchmark than as a hardware benchmark."
Thanks again!
Jose
