i.MX 6Solo timing between DQS and DQ

[sesmor]

Hello NXP!

I need to know t1 and t2 timings, I was trying to find this information in JESD79-3D standart and I couldn't do it. I need DQS out to earliest valid DQ/DM time in writing cycle and DQS out to latest valid DQ/DM time in writing cycle. Can you give me this timings? I have i.MX 6Solo controller (partnumber: MCIMX6S7CVM08AC). DDR3l-800 (AC160/DC90).

[igorpadykov]

Hi Roman

one can check Table 43. DDR3/DDR3L Write Cycle i.MX6DQ Datasheet

http://www.nxp.com/docs/en/data-sheet/IMX6DQCEC.pdf 

and tDQSS, tDSS parameters in Figure 44 — Write

Timing Definition and Parameters in JESD79  DDR3 specification

Best regards
igor
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[sesmor]

No, Table 43 from datasheet showing timings for flash memory, that is not what i needed. tDQSS and tDSS are not the timings I need, because that timings showing how DQS is refering to CK, I need timings showing how DQS is refering to DQ (I showed needed timings in the picture in the first massage).

[igorpadykov]

[sesmor]

This datasheet (IMX6DQCEC) is for I.MX 6Dual/6Quad, I have i.MX 6Solo (IMX6SDLIEC). Do they have the same timings?

[igorpadykov · Accepted solution]

yes MMDC module is same for both processors.

~igor