i.MX 6DQ Plus simultaneously use PCIe and ENET

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i.MX 6DQ Plus simultaneously use PCIe and ENET

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sugiyamatoshihi
Contributor V

Hi,

I'd like to confirm how to configure PCIe and ENET when both use simuletaneously for i.MX6DQ Plus.

Does it still need external 100MHz clock for PCIe and external 125MHz clcok for RGMII when using both simultaneously?

I refer to the below thread. It is for i.MX6DQ.

https://community.nxp.com/message/535599

However, I found the description below in i.MX 6DQ schematics.

Note: ENET_REF_CLK
On the DQP processors this onnection is now
optional, the internal Ethernet PLL can be used
to provide the ENET clock reference

If both need external clock, does BSP implement patches for this use case?

Best Regards,

Sugiyama

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Yuri
NXP TechSupport
NXP TechSupport

Hello,

  For PCIe reference clock is provided, using CLKx_N/P pins of i.MX6, according to 

the Design Checklist recommendations.

  For Ethernet  125 MHz reference clock is required to feed the ENET_REF_CLK input.

This reference clock can be sourced from an external 125 MHz oscillator or an external PHY.

   So, no problem for i.MX 6DQ Plus to use simultaneously PCIe and ENET.

Have a great day,
Yuri

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sugiyamatoshihi
Contributor V

Hi, Yuri,

Thank you for answer.

There seems Linux patch for PCIe is provided. Are there any Linux patch for external clock usage for ENET?

Best Regards,

Sugiyama 

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Yuri
NXP TechSupport
NXP TechSupport

Hello,

 Our Linux BSP supports the SDB, where ENET_REF_CLK is sourced from 

AR8031 PHY. 

i.MX 6QuadPlus SABRE Development Board|NXP 

Regards,

Yuri.

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sugiyamatoshihi
Contributor V

Hi, Yuri,

Thank you for the answer.

One more confirmation. Is this description is correct.

Note: ENET_REF_CLK
On the DQP processors this onnection is now
optional, the internal Ethernet PLL can be used
to provide the ENET clock reference

Does this means PCIe with external clock and RGMII with PLL6 can be operated simultaneously for i.MX 6DQP only?

Best Regards,

Sugiyama

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Yuri
NXP TechSupport
NXP TechSupport

Hello,

Does this means PCIe with external clock and RGMII with PLL6 can be operated simultaneously for i.MX 6DQP only?

No, 

  internal Ethernet PLL can be used to provide the ENET clock reference for the 6QP (instead of 

external clock from PHY).

Regards,

Yuri.

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sugiyamatoshihi
Contributor V

Hi, Yuri,

Thank you for the answer.

I'm sorry I just ask, because I don't have environment for testing of PCIe on i.MX6QP so far. 

I think there is no SW support to use PCIe with external clock and ENET with PLL6 simultaneously on i.MX6QP.

Is it right?

Best Regards,

Sugiyama

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sugiyamatoshihi
Contributor V

Hi, Yuri,

PCIe external clock patch disable ENET below.

When PCIe and ENET use both, is it OK to remove  only below line of patch?

+&fec {

+       status = "disabled";

 

-----------------------------------------------------------------------------------------------------------------

cde0060 MLK-13186-2 arm: imx6qp: add imx6qp standalone pcie dtb

From cde006010b2d436891817982144fba9927a72a61 Mon Sep 17 00:00:00 2001

From: Richard Zhu <hongxing.zhu@nxp.com>

Date: Mon, 5 Sep 2016 16:05:38 +0800

Subject: [PATCH] MLK-13186-2 arm: imx6qp: add imx6qp standalone pcie dtb

 

In order to pass the pcie gen2 compliance tests on imx6qp

sd revb board, add one standalone imx6qp sd ldo pcie dtb

- disalbe fec/sata, because that the fec/sata can't work

when pll6 is in bypass mode.

NOTE: Bypass mode of pll6 is mandatory required when

external oscillator is used as pcie ref clk.

 

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>

(cherry picked from commit 35cd4bdd4d8451a62475ecb922803d656f144bcf)

---

.....

diff --git a/arch/arm/boot/dts/imx6qp-sabresd-ldo-pcie-cert.dts b/arch/arm/boot/dts/imx\

6qp-sabresd-ldo-pcie-cert.dts

new file mode 100644

index 0000000..da6b117

--- /dev/null

+++ b/arch/arm/boot/dts/imx6qp-sabresd-ldo-pcie-cert.dts

@@ -0,0 +1,21 @@

+/*

+ * Copyright (C) 2016 Freescale Semiconductor, Inc.

+ *

+ * This program is free software; you can redistribute it and/or modify

+ * it under the terms of the GNU General Public License version 2 as

+ * published by the Free Software Foundation.

+ */

+

+#include "imx6qp-sabresd-ldo.dts"

+

+&fec {

+       status = "disabled";

+};

+

+&pcie {

+       ext_osc = <1>;

+};

+

+&sata {

+       status = "disabled";

+};

--

-UU-:----F1  0001-MLK-13186-2-arm-imx6qp-add-imx6qp-standalone-pcie-dt.patch   64% L65

Best Regards,

Sugiyama

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Yuri
NXP TechSupport
NXP TechSupport

Why do not try ?  (to remove  only below line of patch +&fec {+       status = "disabled";). 

  Please take into account the following :

1) ENET PLL should be configured after the lvds_clk is configured as clk_in.

2) Before start to link training, PCIe PHY should be re-configured after the RESET

     is cleared if there is a RESET.

Also, please look at the following Setting the iMX6 PCIe Clocks 

~Yuri.

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