i.MX 6 SoloX can ARM Cortex-M4 be turned off

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i.MX 6 SoloX can ARM Cortex-M4 be turned off

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daveebright
Contributor III

We are considering the i.MX 6 SoloX as a processor for a development project.  We like the feature set and smaller size when compared to the other i.MX 6 offerings.  For this development project we have no need for the secondary ARM Cortex-M4 functionality and thus we were wondering if it can be turned off/not used.  If possible we do not want to take the power hit, slow down the boot time loading an image for something that will not be used, or have to add an additional flash chip to our board to store the image (I understand there are other options (load in RAM) which make this unnecessary, but they slow down boot time).  Please let me know if you know if this is possible or if the power usage/additional boot time is so small that it is a non-factor.

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gary_bisson
Senior Contributor III

Hi Dave,

Yes you can use an i.MX6 SoloX without enabling the Cortex-M4. This is why you can see two different device trees in the linux kernel:

http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/arch/arm/boot/dts/imx6sx-sdb-m4.dts...

http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/arch/arm/boot/dts/imx6sx-sdb.dts?h=... 

The first one considers the m4 to be up and therefore disables some peripherals as well as reserves some shared memory for communication between the two cores. Whereas the second dts considers that every peripheral will be used by the A9.

Regarding the M4 state, by default it is disabled (and held in reset), see TRM section 61.7.1 SRC Control Register (SRC_SCR). I don't know how much power is drawn in that state but it should be minimal.

One last thing about the boot time, on the SabreSDB, the M4 uses it's own QSPI device on which the firmware is flashed. That means that there's nothing to load but just the core to enable. I mentions this for your "slower" boot time comment, enabling the m4 when its firmware is in QSPI is a matter of 4 instructions tops so I won't say the boot time is affected by it. But in your case you can get rid of the QSPI component.

Regards,

Gary

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gary_bisson
Senior Contributor III

Hi Dave,

Yes you can use an i.MX6 SoloX without enabling the Cortex-M4. This is why you can see two different device trees in the linux kernel:

http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/arch/arm/boot/dts/imx6sx-sdb-m4.dts...

http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/arch/arm/boot/dts/imx6sx-sdb.dts?h=... 

The first one considers the m4 to be up and therefore disables some peripherals as well as reserves some shared memory for communication between the two cores. Whereas the second dts considers that every peripheral will be used by the A9.

Regarding the M4 state, by default it is disabled (and held in reset), see TRM section 61.7.1 SRC Control Register (SRC_SCR). I don't know how much power is drawn in that state but it should be minimal.

One last thing about the boot time, on the SabreSDB, the M4 uses it's own QSPI device on which the firmware is flashed. That means that there's nothing to load but just the core to enable. I mentions this for your "slower" boot time comment, enabling the m4 when its firmware is in QSPI is a matter of 4 instructions tops so I won't say the boot time is affected by it. But in your case you can get rid of the QSPI component.

Regards,

Gary

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daveebright
Contributor III

Thank you Gary for your detailed answer.  That is the information I was looking for.

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