how to set ENET_CLK to 25MHz ?

[zhaowei]

From the following picture( capture from MCIMX28RM.pdf  --- 10.2.2 Logical Diagram of Clock Domains [Page 885] )

i want to enet_clk output 25MHz instead of 50MHz,how to set register by ENET Controller? i cannot find any register to describe how to divide the ref_enet_pll ?

[gusarambula]

There is a one bit divider that is controlled by register HW_ENET_MAC_RCR[RMII_MODE], when this bit (RMII_MODE) is set to ‘0’, MAC is configured for MII mode and CLK_ENET_OUT will be 25MHz.

[zhaowei]

can we keep rmii mode when set to 25M?thanks.