how to identify which channel(ch_a or ch_b) failed, while the LPDDR4 PHY training failed.

[anhui527]

hi, experts

   our design info : i.MX8MQ with LPDDR4 3GB(Micron 6Gb-die * 4). and we want to change the LPDDR4 3GB(Micron 6Gb-die * 4) device to LPDDR4 2GB(Micron 8Gb-die *2) device. but when i use the DDR stress test tool to verify our new board with new 2GB LPDDR4 device, i get the failed training result.

   coz , on our new-designed PCB , the channel A  has different PCB layout with channel B, we suspect that the failed training result maybe related to our new PCB layout .

   so , we want to know  how to identify which channel(ch_a or ch_b) failed, while the LPDDR4 PHY training failed.

thanks.

[anhui527]

hi,expert

   i upload the related log/RPA/screenshot for this question.

   thanks.

[gusarambula]

Hello An Hui,

The log from the stress test tool should be able to provide more information on the error based in the different tests performed so that may shed some light. Would you please post this log to give it a look? You also can write to individual addresses although that would be just for confirmation on areas where for some reason the memory is not writing or reading correctly.

Regards, 

[anhui527]

hello,gusarambula

   the log is below :

Downloading file 'bin\lpddr4_train1d_string.bin' ..Done

Downloading file 'bin\lpddr4_train2d_string.bin' ..Done

Downloading file 'bin\lpddr4_pmu_train_1d_imem.bin' ..Done

Downloading file 'bin\lpddr4_pmu_train_1d_dmem.bin' ..Done

Downloading file 'bin\lpddr4_pmu_train_2d_imem.bin' ..Done

Downloading file 'bin\lpddr4_pmu_train_2d_dmem.bin' ..Done

Downloading IVT header...Done
Downloading file 'bin\m850_ddr_stress_test.bin' ...Done

Download is complete
Waiting for the target board boot...

********Found PMIC PF0100**********

*************************************************************************

*************************************************************************

*************************************************************************
       MX8 DDR Stress Test V3.10
       Built on Feb  5 2020 14:08:44
*************************************************************************

--Set up the MMU and enable I and D cache--
   - This is the Cortex-A53 core
  - Check if I cache is enabled
  - Enabling I cache since it was disabled
  - Push base address of TTB to TTBR0_EL3
  - Config TCR_EL3
  - Config MAIR_EL3
  - Enable MMU
  - Data Cache has been enabled
  - Check system memory register, only for debug

   - VMCR Check:
   - ttbr0_el3: 0x91d000
   - tcr_el3: 0x2051c
   - mair_el3: 0x774400
   - sctlr_el3: 0xc01815
   - id_aa64mmfr0_el1: 0x1122

  - MMU and cache setup complete

*************************************************************************
            ARM clock(CA53) rate: 800MHz
            DDR Clock: 1600MHz

============================================
        DDR configuration
DDR type is LPDDR4
Data width: 32, bank num: 8
Row size: 16, col size: 10
One chip select is used
Number of DDR controllers used on the SoC: 1
Density per chip select:   2048MB
Density per controller is: 2048MB
Total density detected on the board is: 2048MB
============================================

MX8M: Cortex-A53 is found

*************************************************************************

============ Step 1: DDRPHY Training... ============
---DDR 1D-Training @1600Mhz...
PMU: Error: CA Training Failed.
PMU: ***** Assertion Error - terminating *****
[Result] FAILED

and the RPA excel associated with this failed log is attached.

the result report the CA training failed, we dont know which channel cause this fail.

thanks.