how to generate waveform for LVDS interface based on iMx6 solo

[hailiu]

dear friends,

I am configuring IPU for a 1024x768 LVDS panel for my board based on iMx6 solo processor. So far it is not successful, because there is no signal to be able to observe, I must relay on the SDK code and documents to debug. It seems the documents are not enough. There is no documents for the interface between IPU's DI and LVDS bridge.

I saw in the SDK code that DI0 pin 2 is used to generate hsync, DI0 pin 3 is used to generate  vsync, DI0 pin 15 is used for  data_en. My question is: 

1. what are the signals from DI needed for LVDS bridge?

2. how to generate the waveforms?

3. Can other pins be used for these purpose?

4. Any detailed documents available for IPU?

thank you,

Hai

[hailiu]

Dear igor,

Is my understanding right?

1,the DI clock equals IPU clock if it is generated internally;

2, the IPP_DISP_CLK  equals the clock send to the panel (typically 65MHz).

thanks,

Hai

[hailiu]

Dear igor,

thanks a lot. I will try.

regard!

[igorpadykov]

Hi Hai

all IPU to LDB signal mapping is implemented internally:

 

>Any detailed documents available for IPU?

please use Chapter 38  Image Processing Unit (IPU)

i.MX 6Solo/6DualLite Applications Processor Reference Manual

>how to generate the waveforms?

please try to follow procedures described on p.8 attached README.pdf

and binaries on i.MX6Q Sabre SD board :

https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/sabre-board-for...

Best regards
igor