Hello,
I'm using 8MPLUSLPD4-EVK. The below introduction is copied from the reference manual. How can I enable and disable the interleaving at SPL stage on the board?
Thanks.
9.2.2.1.6 AXI Data Channel Interleaving
A given AXI port (XPI) can access both data channels and low granularity interleaving
between the two data channels is possible by mapping a suitable LSB address bit which is
at the memory burst boundary. In that case, for example, a long AXI burst can be
expanded to HIF commands so that back to back accesses are to alternating data
channels. This setting achieves the highest efficiency possible from a single AXI port.
On the read data path, data order - based on AXI ordering rules - has to be preserved
within each channel and between both channels. The read reorder buffer reorders the data
coming from a given channel. The data ordered from both channels is then reordered by
the data channel reorder logic. Thus two separate data SRAMs are instantiated, one for
each channel, whose outputs are combined to provide a single wide AXI read data
channel.
By setting the correct system mapping, one port can be set to access one data channel and
another port can be set to access the other data channel. This configuration saves logic
area in XPI block.
