The default value of the PWRCTL register(0x3d400030) was 0x1. It was changed to 0x0 to disable selfref. The reference manual explained selfref_en that If true then the DDRC puts the SDRAM into Self Refresh after a programmable number of cycles "maximum idle clocks before Self Refresh (PWRTMG.selfref_to_x32)". This register bit may be reprogrammed during the course of normal operation. Self refresh events were still found with the selfref_en value 0x0. How to prevent reprogramming of this parameter?
self refresh is DRAM itself feature in low power mode. And you said auto-refresh is DDRC site feature at DRAM normal mode. Both of refresh features are aim to protect the data. We do not support disabled the self refresh.