how to config DDR clock of i.mx6q

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how to config DDR clock of i.mx6q

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geekdarcy
Contributor III
Hi everyone,
I'm developing a new board based on the IMX6Q.
We have make the DDR's clock root from 528M successfully.The uboot's version  what we use is 2009.08.
We want to make DDR running at 400M for some reason.

We have read how to change DDR clock of i.mx6 . Many efforts have been tried according to the thread.

but the u-boot can't start up.

Is the DCD table as defined in the uboot source file "board/freescale/mx6q_sabresd/flash_header.S" my only point for DDR configuration?

By the way, could I change ddr clock after boot ?

Does anyone know what I am doing wrong? Any clue about that error?

Can you help us ?
Yours sincely.

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hukun
Contributor I

I'm face the same problem  too. any thing updated? Thanks a lot.

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hung_nguyen
Contributor I

When we have moved our DDR config from 528Mhz to 396Mhz, we found it necessary to gather new DDR calibration timings.  We ran the NXP DDR Stress tool calibration at 396Mhz and inserted those into our Uboot DCD.

We experienced kernel lockups and other strange behavior until we recalibrated.

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art
NXP TechSupport
NXP TechSupport

Q. Is the DCD table as defined in the uboot source file "board/freescale/mx6q_sabresd/flash_header.S" my only point for DDR configuration?

A. This is the only point to configure DDR at startup time.

Q. By the way, could I change ddr clock after boot ?

A. Yes, it is possible. Please refer to the Sections 2.5.3 "CPU Frequency Scaling (CPUFREQ)" and 2.5.4 "Dynamic Bus Frequency" of the attached document.


Have a great day,
Artur

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geekdarcy
Contributor III

Hi Artur,

       Thanks for reply.

       How  to make the DDR's clock root from 400M ?  Could you give me some tips? 

       According to the CCM Clock Tree,we have switched  pre_periph_clk  from 528M PLL2 to 396M PFD. 
       And we have adjusted DDR script to make it work at 400M.

       But  the u-boot can't start up.

       What's more, which Reference document are you taking about for  the second question ? 

       We can't find the Sections 2.5.3 "CPU Frequency Scaling (CPUFREQ)" and 2.5.4 "Dynamic Bus Frequency".

       Could you kindly tell me which document do you mean?

       Have a good day.

      Yours sincely.

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art
NXP TechSupport
NXP TechSupport

The DDR clock cannot operate at exactly 400MHz, actually, it can be either 528MHz or 396MHz. For the document I'm referring to, please find it attached once again.

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geekdarcy
Contributor III

Hi Artur,

       Thanks for reply.

       I have made the DDR's clock root from 396M by modify  DCD ITEMS successfully.

       But the system hangs when kernel  is starting. 

       Do you know what I am doing wrong? Any clue about that error?
       Serial output is as follows:
U-Boot 2009.08 (Feb 18 2019 - 03:06:52)

U-Boot code: 27800640 -> 27833200 BSS: -> 2786D348
CPU: Freescale i.MX6 family TO1.5 at 792 MHz
Thermal sensor with ratio = 184
Temperature: 41 C, calibration data 0x58b4f469
mx6q pll1: 792MHz
mx6q pll2: 528MHz
mx6q pll3: 480MHz
mx6q pll8: 50MHz
ipg clock : 49500000Hz
ipg per clock : 49500000Hz
uart clock : 80000000Hz
cspi clock : 60000000Hz
ahb clock : 99000000Hz
axi clock : 198000000Hz
emi_slow clock: 99000000Hz
ddr clock : 396000000Hz
usdhc1 clock : 198000000Hz
usdhc2 clock : 198000000Hz
usdhc3 clock : 198000000Hz
usdhc4 clock : 198000000Hz
nfc clock : 24000000Hz
Board: i.MX6Q-SABRESD: unknown-board Board: 0x63015 [POR ]
Boot Device: MMC
I2C: ready
RAM Configuration:
Bank #0: 10000000 1 GB
MMC: FSL_USDHC: 0,FSL_USDHC: 1,FSL_USDHC: 2,FSL_USDHC: 3
*** Warning - bad CRC or MMC, using default environment

In: serial
Out: serial
Err: serial
config_ipu_di_clk: freq = 108000000.
wait for pll5 lock.
config_ipu_di_clk: set pll5 clock to 216000000Hz.
i2c: I2C1 SDA is low, start i2c recovery...
I2C1 Recovery success
Found PFUZE100! deviceid=10,revid=21
Net: got MAC address from IIM: 00:00:00:00:00:00
FEC0 [PRIME]
### main_loop entered: bootdelay=3

### main_loop: bootcmd="run bootcmd_mmc"
Hit any key to stop autoboot: 0
mmc3(part 0) is current device

MMC read: dev # 3, block # 2048, count 10496 ... 10496 blocks read: OK
* kernel: default image load address = 0x10800000
## Booting kernel from Legacy Image at 10800000 ...
Image Name: Linux-3.0.35-2666-gbdde708
Image Type: ARM Linux Kernel Image (uncompressed)
Data Size: 4184384 Bytes = 4 MB
Load Address: 10008000
Entry Point: 10008000
Verifying Checksum ... OK
kernel data at 0x10800040, len = 0x003fd940 (4184384)
## No init Ramdisk
ramdisk start = 0x00000000, ramdisk end = 0x00000000
Loading Kernel Image ... OK
OK
kernel loaded at 0x10008000, end = 0x10405940
## Transferring control to Linux (at address 10008000) ...

Starting kernel ...

Uncompressing Linux... done, booting the kernel.
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