how to calculate the time in table 44-8. MMDC Refresh Scheme

[masatsuguyamada]

Hi,
I have a question about i.MX6 document,
http://www.nxp.com/assets/documents/data/en/reference-manuals/IMX6DQRM.pdf
p.3848, Table 44-8. MMDC Refresh Scheme.

The column "Description" of the table describes,

Option number	Description	REF_SEL
1	31,250 ns	64 KHz
2	15,625 ns	32 KHz

I understood the interval time in "Description" is related to REF_SEL, but I couldn't understand how to calculate.

My question is how to calculate the interval time described in "Description".
It seems the time is not inverse number of the frequency(REF_SEL).

However this interval time seems right from my experiment using DDR Stress Test.
I tried two test case (REFR is same value for purpose),
(1) REFR=0x3 REF_SEL=0 (64KHz)
(2) REFR=0x3 REF_SEL=1 (32KHz)
and (1) was failed within 400~500 loops, (2) was continued over 1000 loops.

Thanks in advance,
Yamada

[Yuri]

Hello

   I think it would be better to look at tables in section 44.12.9 [MMDC Core Refresh

Control Register (MMDCx_MDREF)] of the RM.

Have a great day,
Yuri

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[masatsuguyamada]

Thanks for advice! actually, I tried the Stress Test with REF_SEL=32/64KHz, and
when I changed REF_SEL to 64KHz from 32KHz, the system became easier to fail.

Also before my trial, I thought the refresh rate of
(a) REF_SEL=32KHz REFR=0x7 (8 Refreshes)
(b) REF_SEL=64KHz REFR=0x3 (4 Refreshes)
will be same, but in the Stress Test, (a) was stable, but (b) was failed at early loop (100~200 loops).

So I wish to know how REF_SEL affect to refresh rate. I thought if Description column in the Table 44-8 is true, above result can be explained.

Regards,
Yamada

[Yuri]

Hello,

  Your understanding of how the refresh rate should be calculated is correct,

assuming that DRAM part should be fully refreshed within a specified Refresh

Window (usually 64 ms, but LPDDR2 has temperature dependence here, may

be 32 ms).

  Configurations

(a) REF_SEL=32KHz with REFR=0x7 (8 Refreshes)

and

(b) REF_SEL=64KHz (both edges of 32KHz is involved) with REFR=0x3 (4 Refreshes)

are the same. NXP recommends 32KHz variant using.

  “The way that parameter tREFI is determined (for LPDDR2) is to count up all the refreshes within

a specified Refresh Window (32 ms for T<85C), and then divide 32 ms by the number received to get

the average tREFI.”

  Is Your DRAM - LPDDR2 ?

Please double check design using the following design checklist

https://community.nxp.com/docs/DOC-93819 

Regards,

Yuri.

[masatsuguyamada]

Thank you very much! My question about REF_SEL / REFR  was resolved.

The HW structure is following ( using DDR3 ).
- i.MX6  ( MCIMX6Q7CVT08AC )
- DDR3 DRAM ( mt41k256m16ha,  https://www.micron.com/parts/dram/ddr3-sdram/mt41k256m16ha-125-it )

Excel file in the linked site will be helpful, I will check it with HW team.

Regards,
Yamada