how is dsi hs clk calculated

[gmoore18]

Hello, so I have a display that's running at 60hz It's dsi-hs-clk = 477MHz by manufacturer and i'm curious how it was calculated

I've found following formulas that calculate the hs clk:

h_active total - h_active + HBP + HFP + HSW
v_active total - v_active + VBP + VFP + VSW
PCLK (disp-pll-clk & disp-vclk) = fps * h_active total * v_active total (output in Hz)
Pixel time = 1/PCLK (output in seconds)

dsi_hs_clk = (PCLK * bpp)/lane_number

manufacturer set PCLK is 64MHz for 60 fps

bpp is 32, 4 lanes

so 64x32/4=512MHz

why doesn't it get accurate value? Are the formulas wrong?

also, what could ECLK be (it's set to 70MHz)

[igorpadykov]

Hi Grady

one can look at

https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/Setting-i-MX8M-Mini-and-Nano-MIPI-DPHY-C...

Best regards
igor

[gmoore18]

hello it is the same formula as i used (bit_clk = pixel clock * bits per pixel / number of lanes)

so bit_clk = 64 * 32 / 4 = 512MHz

but it's set to 477 by the manufacturer. how can the display run at a lower rate?