enable L2 cache of i.mx6

[xiuqingchang]

I have learned MX6Q PCIe EP/RC Validation and Throughput,and know the write speed is 109MB/s and read speed is 29MB/s when cache is disabled,but when cache is enabled the write speed can reach up to about 298MB/s and read speed can reach up to 100MB/s ,please tell me how to enable the cache?thanks

[carlpii]

The i.MX6Q PCIe EP/RC Validation and Throughput page seems misleading when it refers to "cache is enabled" or "cache is not enabled".  In all cases, both the L1 & L2 caches are enabled.  I believe the difference between the two is how the iATU region in the i.MX6 address space is mapped by the MMU.  Specifically for Linux, that would mean either using ioremap() which maps the region as Device memory ("cache is not enabled") or using ioremap_cache() which maps the region as Cacheable ("cache is enabled").  I was able to replicate the performance results by switching between these in some test code I wrote.

Unfortunately, the cacheable approach does create coherency issues you will need to handle on your own (cache flushes and invalidates).  The endpoint driver code in pcie-imx6.c does not include that.  I have not tried to address this in my test code.

-Carl

[igorpadykov]

Hi xiuqing

linux always uses l2 cache, except probably in low power modes.

Seems it could be disabled only in bare metal tests.

Best regards
igor
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[xiuqingchang]

and I have learned L2 cache(PL310) is enabled in kernel (arch/arm/mm/cache-l2x0.c),but i enable or disable the cache here(cache-l2x0.c),the write speed and read speed don't change,please tell me how to enable the cache to improve the speed,thanks