ecspi2 on the i.MX8 not functioning?

[GregT]

I am trying to use the spi-imx.c driver but it doesn't seem like the registers are responding.  Is there an enable or voltage regulator required to use the ecspi?  For example I try to write to the ecspi control register and it does not stick in the register.  I used devmem2 that comes with the yocto build for the Compulabs cl-som-imx8.  The driver doesn't seem to be able to write to this register either.  See below.  It tries to write 0xf091f5 but it stays at 0xF091F1.  FYI, I am not using dma.

root@cl-som-imx8:~# devmem2 0x30830008 w 0x0000010000F091F5
/dev/mem opened.
Memory mapped at address 0xffff84016000.
Read at address 0x30830008 (0xffff84016008): 0x0000010000F091F1
Write at address 0x30830008 (0xffff84016008): 0x0000010000F091F5, readback 0x0000010000F091F5
root@cl-som-imx8:~# devmem2 0x30830008 w
/dev/mem opened.
Memory mapped at address 0xffff91e4e000.
Read at address 0x30830008 (0xffff91e4e008): 0x0000010000F091F1

Below is some debug output from the spi-imx.c driver also tries to write a value to this register.  But it does not stick.

Dec 20 20:11:32 cl-som-imx8 user.debug kernel: [ 575.886816] spidev spi32766.0: spi_imx_setup: mode 0, 16 bpw, 10000000 hz
Dec 20 20:11:32 cl-som-imx8 user.debug kernel: [ 575.886830] spidev spi32766.0: 16 bits per word
Dec 20 20:11:32 cl-som-imx8 user.debug kernel: [ 575.887069] spidev spi32766.0: xfer len 4 tx 16bits 0 usec 10000000Hz
Dec 20 20:11:32 cl-som-imx8 user.debug kernel: [ 575.887076] spidev spi32766.0: xfer len 4 rx 16bits 0 usec 10000000Hz
Dec 20 20:11:32 cl-som-imx8 user.debug kernel: [ 575.887103] spidev spi32766.0: spi_imx_setupxfer: NEW mode 0, 16 bpw, 10000000 hz, conf
ig.bpw 16, config.speed_hz 10000000, spi_imx->usedma 0
Dec 20 20:11:32 cl-som-imx8 user.debug kernel: [ 575.887111] spi_imx 30830000.ecspi: mx51_ecspi_clkdiv: fin: 200000000, fspi: 10000000,
post: 1, pre: 9
Dec 20 20:11:32 cl-som-imx8 user.debug kernel: [ 575.887119] spi_imx 30830000.ecspi: spi_imx_push: count 4, txfifo 0, txfifosize 64
Dec 20 20:11:32 cl-som-imx8 user.debug kernel: [ 575.887125] spi_imx 30830000.ecspi: mx51_ecspi_trigger: trigger value 0xf091f5
Dec 20 20:11:32 cl-som-imx8 user.debug kernel: [ 575.887132] spi_imx 30830000.ecspi: mx51_ecspi_intctrl: enable 0x1, val 0x1
Dec 20 20:11:32 cl-som-imx8 user.debug kernel: [ 575.887139] spidev spi32766.0: spi_imx_pio_transfer: count 0, timeout 500

[igorpadykov]

Hi Greg

as described in cl-som-imx8 manual there are only ecspi1,3 ports on board:

https://www.compulab.com/wp-content/uploads/2018/01/cl-som-imx8_reference-guide_2018-01-09.pdf 

for ecspi2 example one can look on imx8mq-nitrogen8m.dts

linux-imx6/imx8mq-nitrogen8m.dts at boundary-imx_4.9.x_2.0.0_ga · boundarydevices/linux-imx6 · GitHu... 

Best regards
igor
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[GregT]

Hi Igor,

We were told that the version 1.0 of the Compulab cl-som-imx8 that we are using has the ecspi2 connected.  We have been able to use the same lines as gpio and do our own bit bang and it works.  We just wanted to be able to use the ecspi controller to make sure we had good timing and could take advantage of a spidev driver in Linux.  Is it possible the  ecspi2 controller is not activated or powered even though the lines are connected out of the SOM?  Maybe a device tree entry could fix it?  I do have an ongoing issue with Compulab on this problem.

Thanks,

Greg

[igorpadykov]

Hi Greg

this board was developed and supported by variscite, so it may be posted on its tech support

Variscite Support Center - Variscite 

>Maybe a device tree entry could fix it?

I think this is possible, please try suggested imx8mq-nitrogen8m.dts example

Best regards
igor

[GregT]

Thank you Igor!

This resolved my problem.  The imx8mq-nitrogen8m.dts example showed I had the wrong irq number in my device tree.  It is now getting the read interrupts.  The data doesn't look correct but at least the driver seems to be functioning.

Thanks again,

Greg

[GregT]

All is working now.  To fix the data problem I had to change the phase of the spi controller so input is sampled on trailing clock edge.