eMMC4.4/4.41 (Dual Data Rate) AC Timing of i.MX6DL

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eMMC4.4/4.41 (Dual Data Rate) AC Timing of i.MX6DL

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宗標廖
Contributor V

Hello Community

Figure 41. eMMC4.4/4.41 Timing and Table 52. eMMC4.4/4.41 Interface Timing Specification in IMX6SDLAEC(Rev.7) describe the AC timing of eMMC4.4/4.41 DDR mode.

But it has no information about Clock Low Time and Clock High Time like Table 53. SDR50/SDR104 Interface Timing Specification.

So could you offer me Clock Low Time and Clock High Time information of eMMC4.4/4.41 (Dual Data Rate) AC Timing?

Thank you!

ZongbiaoLiao

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi ZongbiaoLiao

i.MX6SDL complies with eMMC4.4/4.41 Interface Timing Specification

which describes this parameter as Clock duty cycle: 45(min)-55(max) %

in Table 115 — High-speed dual rate interface timing

www.jedec.org/sites/default/files/docs/JESD84-A441.pdf

Best regards
igor
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宗標廖
Contributor V

Hi igor

Thank you very much!

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