eMMC does not get detected on iMX8M mini

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eMMC does not get detected on iMX8M mini

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iogenies
Contributor I

We have designed a custom board with iMX8M mini. The baseline reference is iMX8M mini DDR4 EVK. 

We are facing issue with eMMC card. The connections and layout referred for eMMC section is ok iMX8M mini LPDDR EVK. Also, in place of Sandisk we have used Toshiba (Kioxia) eMMC - THGBMNG5D1LBAIL. 

We are facing issues both in u-boot and Kernel, which initializing this eMMC. The pinmux setting are same as for iMX8M mini LPDDR4 evk. 

Here is the log with MMC_TRACE enabled in uboot, 

mmc1 is current device
u-boot=> mmc dev 2
mmc@30b60000: No vmmc supply
mmc@30b60000: No vqmmc supply
clock is disabled (0Hz)
selecting mode MMC legacy (freq : 25 MHz)
clock is enabled (400000Hz)
CMD_SEND:0
ARG 0x00000000
MMC_RSP_NONE
CMD_SEND:8
ARG 0x000001aa
RET -110
CMD_SEND:55
ARG 0x00000000
RET -110
CMD_SEND:0
ARG 0x00000000
MMC_RSP_NONE
CMD_SEND:1
ARG 0x00000000
MMC_RSP_R3,4 0x00ff8080
CMD_SEND:1
ARG 0x40300000
MMC_RSP_R3,4 0x00ff8080
CMD_SEND:0
ARG 0x00000000
MMC_RSP_NONE
CMD_SEND:1
ARG 0x40300000
MMC_RSP_R3,4 0x00ff8080
CMD_SEND:1
ARG 0x40300000
MMC_RSP_R3,4 0x00ff8080
CMD_SEND:1
ARG 0x40300000
MMC_RSP_R3,4 0xc0ff8080
CMD_SEND:2
ARG 0x00000000
MMC_RSP_R2 0x11010030
0x30344741
0x3002a218
0xd61f2700

DUMPING DATA
000 - 11 01 00 30
004 - 30 34 47 41
008 - 30 02 a2 18
012 - d6 1f 27 00
CMD_SEND:3
ARG 0x00010000
MMC_RSP_R1,5,6,7 0x00000500
CMD_SEND:9
ARG 0x00010000
MMC_RSP_R2 0xd05e0032
0x0f5903ff
0xffffffe7
0x92400000

DUMPING DATA
000 - d0 5e 00 32
004 - 0f 59 03 ff
008 - ff ff ff e7
012 - 92 40 00 00
selecting mode MMC legacy (freq : 25 MHz)
CMD_SEND:7
ARG 0x00010000
MMC_RSP_R1,5,6,7 0x00000700
CMD_SEND:8
ARG 0x00000000
RET -70
mmc_init: -70, time 168

 

The pin_mux settings are as below - 

pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
>;
};

pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
>;
};

pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
>;
};

DTS - 

&usdhc3 {

pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
bus-width = <8>;
non-removable;

status = "okay";
};

Could anyone please help, why the error for CMD 8 is -70?  

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weidong_sun
NXP TechSupport
NXP TechSupport

Hi iogenies,

    By default, i.MX8MMD4-EVK doesn't initialize uSDHC2 clock in spl.c of board/freescale/imx8mm-evk. So you need to initialize it manually.

See int board_mmc_init(bd_t *bis) function, please!

/*for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {*/

for (i = 0; i < 2; i++) {

if evk is DDR4 version, CONFIG_SYS_FSL_USDHC_NUM=1, if evk is LPDDR4 version CONFIG_SYS_FSL_USDHC_NUM=2, the reson for this is that no eMMC is supported on D4-EVK.

   On your board, eMMC is supported, just like on LPDDR4-EVK, so you should modify above source code.

 

Hope this can help you.

Have a nice day!

B.R,

weidong

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iogenies
Contributor I

Thank you Weidong, for the reply. 

Other change we found in board is, we have NVCC_NAND connected to 3.3V rail (same as DDR4). However, eMMC VQMMC is operating at 1.8V. As per our understanding and datasheet, iMX8M MMC interface can operate at 1.8V. This configuration can be done using VSELECT register. 

Please confirm, if this understanding is correct. 

Help us know the additional configuration, if any, needs to be done in u-boot and Kernel, for this. 

Thanks.  

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